Semiconductor chip package having heat dissipating structure

Patent metadata

Field	Value
Publication number	US-10204848-B2
Application number	US-201815947877-A
Country	US
Kind code	B2
Filing date	Apr 9, 2018
Priority date	Aug 4, 2016
Publication date	Feb 12, 2019
Grant date	Feb 12, 2019

Abstract

Disclosed herein is a semiconductor chip package having a heat dissipating structure. The semiconductor chip package including: a semiconductor chip configured such that a plurality of terminals protrudes from the upper surface thereof; lead frames connected to the terminals located on the upper surface of the semiconductor chip; and a package body configured to protect the semiconductor chip and the lead frames and to form the outside shape of the semiconductor chip package, and formed by molding. The lower surfaces of the lead frames are exposed to the outside. The lower surface of the package body is partially cut out such that the bottom surface of the semiconductor chip is exposed to the outside.

First claim

What is claimed is:

1. A semiconductor chip package comprising:
a semiconductor chip configured such that terminals are formed on an upper surface thereof;
lead frames indirectly connected to the terminals located on the upper surface of the semiconductor chip;
a substrate directly attached to the terminals of the semiconductor chip, and configured to enable the lead frames to be indirectly connected to the terminals; and
a package body configured to protect the semiconductor chip and the lead frames and to form an outside shape of the semiconductor chip package, and formed by molding;
wherein lower surfaces of the lead frames are exposed to an outside; and
wherein a lower surface of the package body is partially cut out such that a bottom surface of the semiconductor chip is exposed to the outside.

2. The semiconductor chip package of claim 1 , wherein the terminals protrude from the upper surface of the semiconductor chip.

3. The semiconductor chip package of claim 1 , wherein the substrate comprises:
a lower metal configured to enable the terminals to be connected to the lead frames;
an upper metal configured such that one surface thereof is exposed via the upper surface of the package body, thereby enabling heat dissipation to be performed; and
an insulation adhesive provided between the lower metal and the upper metal, and configured to enable heat transfer between the lower metal and the upper metal.

4. The semiconductor chip package of claim 1 , wherein the upper surfaces of the lead frames are disposed flush with upper surfaces of the terminals.

5. The semiconductor chip package of claim 1 , wherein the semiconductor chip comprises a plurality of semiconductor chips.

Assignees

• Jmj Korea Co Ltd

Inventors

• Choi Yunhwa
• Cho Jeonghun

Classifications

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title

• H10W70/468

  Circuit boards · CPC title