Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11387144-B2
Application number	US-202017070012-A
Country	US
Kind code	B2
Filing date	Oct 14, 2020
Priority date	Dec 1, 2017
Publication date	Jul 12, 2022
Grant date	Jul 12, 2022

Abstract

Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises providing a layout comprising a first group that includes first and second patterns and a second group that includes third and fourth patterns, examining a bridge risk region in the layout, biasing one end of at least one of the first and third patterns, and forming first to fourth conductive patterns by respectively using the first to fourth patterns of the layout. The one end of at least one of the first and third patterns are adjacent to the bridge risk region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate; and
first, second, third, and fourth conductive patterns on the substrate, the first to fourth conductive patterns extending in parallel to each other in a first direction and being sequentially arranged in a second direction crossing the first direction,
wherein the third conductive pattern comprises on one side a first extension protruding toward the first conductive pattern and not contacting the second conductive pattern, and
wherein the second conductive pattern comprises on one side a second extension protruding toward the fourth conductive pattern and not contacting the third conductive pattern,
wherein the first extension and the second extension are spaced apart from each other in the first direction,
wherein the first extension is aligned in the second direction with one end of the first conductive pattern and the second extension is aligned in the second direction with one end of the fourth conductive pattern such that the one end of the first conductive pattern and the one end of the fourth conductive pattern are also spaced apart from each other in the first direction.

2. The device of claim 1 , wherein neighboring ones of the first to fourth conductive patterns are arranged at substantially the same pitch.

3. The device of claim 1 , further comprising a fifth conductive pattern adjacent in the first direction to the fourth conductive pattern,
wherein the second conductive pattern further comprises on its one side a third extension protruding toward the fifth conductive pattern,
the third extension being aligned in the second direction with one end of the fifth conductive pattern.

4. The device of claim 1 , wherein a first line in the second direction passing through the one end of the first conductive pattern and a second line in the second direction passing through the one end of the fourth conductive pattern are spaced apart from each other in the first direction.

5. A semiconductor device, comprising:
a substrate; and
first, second, third, and fourth conductive patterns on the substrate, the first to fourth conductive patterns extending in parallel to each other in a first direction and being sequentially arranged in a second direction crossing the first direction,
wherein a first side of the third conductive pattern faces a second side of the second conductive pattern,
wherein the third conductive pattern comprises a first extension protruding from the first side toward the second side of the second conductive pattern, the first extension being spaced apart from the second side,
wherein the second conductive pattern comprises a second extension protruding from the second side toward the first side of the third conductive pattern, the second extension being spaced apart from the first side,
wherein the first extension and the second extension are offset from each other in the first direction,
wherein the first extension is aligned in the second direction with one end of the first conductive pattern and the second extension is aligned in the second direction with one end of the fourth conductive pattern such that the one end of the first conductive pattern and the one end of the fourth conductive pattern are also offset from each other in the first direction.

6. The device of claim 5 , wherein neighboring ones of the first to fourth conductive patterns are arranged at substantially the same pitch.

7. The device of claim 6 , further comprising:
a fifth conductive pattern adjacent in the first direction to the fourth conductive pattern,
wherein the second conductive pattern further comprises a third extension protruding from the second side toward the first side of the third conductive pattern,
the third extension being aligned in the second direction with one end of the fifth conductive pattern.

8. The device of claim 1 , wherein a first line in the second direction passing through the one end of the first conductive pattern and a second line in the second direction passing through the one end of the fourth conductive pattern are offset from each other in the first direction.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoon Daeho
• Jeon Daeseon
• Choi Jaeyoung

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H10W20/067 Primary

  by modifying the pattern of conductive parts · CPC title

• H10W20/089 Primary

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10D84/00

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title