Device manufacture and packaging method thereof

Patent metadata

Field	Value
Publication number	US-2016276266-A1
Application number	US-201514658540-A
Country	US
Kind code	A1
Filing date	Mar 16, 2015
Priority date	Mar 16, 2015
Publication date	Sep 22, 2016
Grant date	—

Abstract

Some embodiments of the present disclosure provide a semiconductive device. The semiconductive device includes a first conductive layer and a second conductive layer above the first conductive layer. The second conductive layer includes a first portion and a second portion protruding from the first portion. A via structure is under the second conductive layer and on top of the first conductive layer. The via structure is substantially aligned vertically with the second portion.

First claim

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15 . A method of manufacturing a semiconductive device, comprising:
forming a top dielectric layer over a bottom dielectric layer having a recess; forming a photosensitive layer over the top dielectric layer; and exposing a first portion and a second portion of the photosensitive layer, wherein the second portion protruding from the first portion in a lateral direction, and the second portion substantially overlaps with the recess.

16 . The method of claim 15 , wherein the method of exposing the first portion of the photosensitive layer is simultaneously performed with the method of exposing the second portion of the photosensitive layer.

17 . The method of claim 15 , wherein the method of exposing the first portion of the photosensitive layer is subsequently followed by the method of exposing the second portion of the photosensitive layer.

18 . The method of claim 15 , further comprising forming a conductive material inside the recess.

19 . The method of claim 18 , further comprising forming a conductive layer over the recess, wherein a thickness of the conductive layer is more than about 2 micrometers.

20 . The method of claim 15 , further comprising removing a portion of the top dielectric layer under the first portion and the second portion of the photosensitive layer.

21 . A method of manufacturing a semiconductive device, comprising:
forming a top dielectric layer over a bottom dielectric layer having a recess, the top dielectric layer having a thickens more than about 2 micrometers; and patterning the top dielectric layer to form a first portion and a second portion, wherein the second portion protruding from the first portion in a lateral direction, and the second portion substantially overlaps with the recess.

22 . The method of claim 21 , wherein the patterning the top dielectric layer comprises patterning the first portion and the second portion simultaneously.

23 . The method of claim 22 , wherein the patterning the first portion and the second portion simultaneously comprises:
forming a photosensitive layer over the top dielectric layer; and exposing a portion of the photosensitive layer according to the first portion and the second portion of the top dielectric layer in one operation.

24 . The method of claim 22 , wherein the patterning the first portion and the second portion simultaneously comprises removing a portion of the top dielectric layer to form the first portion and the second portion.

25 . The method of claim 21 , wherein the patterning the top dielectric layer comprises patterning the first portion and the second portion sequentially.

26 . The method of claim 25 , wherein the patterning the first portion and the second portion sequentially comprises:
forming a photosensitive layer over the top dielectric layer; exposing a portion of the photosensitive layer according to a contour of the first portion; and exposing a portion of the photosensitive layer according to a contour of the second portion after the exposing the portion of the photosensitive layer according to the contour of the first portion.

27 . The method of claim 25 , wherein the patterning the first portion and the second portion sequentially comprises:
removing a portion of the top dielectric layer to form the first portion; and removing a portion of the top dielectric layer to form the second portion after removing the portion of the top dielectric layer to form the first portion.

28 . A method of manufacturing a semiconductive device, comprising:
forming a first conductive layer; forming a via structure on top of the first conductive layer, the via structure comprising a lateral side; forming a second conductive layer over the via structure, the second conductive layer comprising a lateral boundary of a first region connected to the lateral side of the via structure such that a first portion of the lateral boundary is aligned vertically with the lateral side of the via structure.

29 . The method of claim 28 , further comprising forming a protective layer over the first conductive layer and surrounding the via structure in proximity to the first conductive layer.

30 . The method of claim 29 , wherein the forming the protective layer comprises forming a nitride layer.

31 . The method of claim 28 , wherein the first portion of the lateral boundary comprises a protruding portion.

32 . The method of claim 28 , wherein the forming the second conductive layer further comprises forming a second region distanced from the first portion of the lateral boundary by a predetermined value.

33 . The method of claim 28 , wherein the forming the via structure comprises filling conductive material similar to that of the second conductive layer into a via opening.

34 . The method of claim 28 , wherein the lateral side of the via structure is formed to be in contact with the first conductive layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Chien-Hsuan

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/0886

  involving forming a via in a via-level dielectric prior to deposition of a trench-level dielectric · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title