FET capacitor circuit architectures for tunable load and input matching

Patent metadata

Field	Value
Publication number	US-11380679-B2
Application number	US-201816141641-A
Country	US
Kind code	B2
Filing date	Sep 25, 2018
Priority date	Sep 25, 2018
Publication date	Jul 5, 2022
Grant date	Jul 5, 2022

Abstract

Integrated circuit architectures for load and input matching that include a capacitance selectable between a plurality of discrete levels, which are associated with a number of field effect transistors (FET) capacitor structures that are in an on-state. The capacitance comprises a metal-oxide-semiconductor (MOS) capacitance associated with each of the FET capacitor structures, and may be selectable through application of a bias voltage applied between a first circuit node and a second circuit node. Gate electrodes of the FET capacitor structures may be coupled in electrical parallel to the first circuit node, while source/drains of the FET capacitor structures are coupled in electrical parallel to the second circuit node. Where the FET capacitor structures have different gate-source threshold voltages, the number of FET capacitor structures in the on-state may be varied according to the bias voltage, and the capacitance correspondingly tuned to a desired value. The FET capacitor structures may be operable in depletion mode and/or enhancement mode.

First claim

What is claimed is:

1. A radio frequency (RF) transmitter, comprising:
an antenna;
a power amplifier; and
an RF matching circuit coupled between the power amplifier and the antenna, wherein the RF matching circuit has a tunable capacitance, and wherein the RF matching circuit comprises:
a plurality of field effect transistor (FET) capacitor structures, wherein:
individual ones of the FET capacitor structures comprise a source, a drain, and a gate electrode, wherein the source and drain of individual ones of the FET capacitor structures are coupled through a Group III-nitride (III-N) material;
the gate electrode of individual ones of the FET capacitor structures are coupled in electrical parallel to a first circuit node to convey a radio frequency (RF) signal wherein a first of the FET capacitor structures comprises a first gate electrode separated from the III-N material by a first distance and a second of the FET capacitor structures comprises a second gate electrode separated from the III-N material by a second distance, different than the first distance, and wherein at least one of the source and the drain of individual ones of the FET capacitor structures are coupled to a second circuit node to convey the RF signal;
a gate-source threshold voltage of the FET capacitor structures varies across the plurality; and
a number of the FET capacitor structures in an on-state is to vary a tunable capacitance as a function of a bias voltage between the first and second circuit nodes relative to a threshold voltage of individual ones of the FET capacitor structures.

2. The RF transmitter of claim 1 , wherein the tunable capacitance comprises a MOS capacitance of the plurality of FET capacitor structures, and wherein the gate-source threshold voltage varies by less than 10 volts.

3. The RF transmitter of claim 2 , wherein the gate-source threshold voltage varies over a range of at least 4 volts that includes 0 volts, and wherein at least one of the FET structures is operable in an enhancement mode.

4. The RF transmitter of claim 3 , wherein at least some of the FET capacitor structures are operable in a depletion mode and the gate-source threshold voltage varies over a range that includes −3 volts.

5. The RF transmitter of claim 4 , wherein a maximum MOS capacitance of individual ones of the FET capacitor structures varies over the plurality.

6. The RF transmitter of claim 1 , wherein at least some of the FET capacitor structures further comprise a gate dielectric material between the gate electrode an the III-N material.

7. The RF transmitter of claim 1 , wherein:
the III-N material is a first III-N material comprising Ga and N;
a second III-N material is between a gate dielectric material and the first III-N material;
the second III-N material comprises more Al than the first III-N material; and
a c-plane of the first and second III-N materials is no more than 10° from parallel to plane of an underlying substrate.

8. The RF transmitter of claim 7 , wherein the source and the drain of the FET capacitor structures further comprises a third III-N material and wherein a source of the first of the FET capacitor structures is in direct contact with a drain of the second of the FET capacitor structures.

9. The RF transmitter of claim 1 , further comprising a battery coupled to the RF transmitter.

10. An integrated circuit (IC) with tunable capacitance, comprising:
a first circuit node to convey a radio frequency (RF) signal, the first circuit node coupled in electrical parallel to gate electrodes of a plurality of Group III-nitride (III-N) field effect transistor (FET) capacitor structures, wherein individual ones of the III-N FET capacitor structures further comprise:
a source and drain coupled through a III-N material; and
a gate electrode between the source and the drain, wherein a first of the FET capacitor structures comprises a first gate electrode separated from the III-N material by a first distance and a second of the FET capacitor structures comprises a second gate electrode separated from the III-N material by a second distance, different than the first distance;

a second circuit node to convey the RF signal, the second circuit node coupled to at least one of a source and a drain of individual ones of the III-N FET capacitor structures, wherein:
a threshold voltage of the III-N FET capacitor structures varies across the plurality; and
the tunable capacitance is to vary with a number of the III-N FET capacitor structures that are in an on-state as a function of a bias voltage between the first and second circuit nodes relative to the threshold voltage of individual ones of the III-N FET capacitor structures.

11. The IC of claim 10 , wherein:
the tunable capacitance comprises a MOS capacitance of the plurality of III-N FET capacitor structures;
the threshold voltage varies over a range less than 10V; and
at least some of the III-N FET capacitor structures are operable in a depletion mode.

12. A method of tuning a capacitance of a radio frequency (RF) integrated circuit, the method comprising:
applying the RF signal to the first circuit node of claim 10 ; and
varying a number of the FET capacitor structures in an on-state by varying the bias voltage between the first circuit node and the second circuit node.

13. A method of forming an integrated circuit (IC), the method comprising:
receiving a workpiece comprising a first III-N material under a second III-N material;
forming a first FET capacitor structure within a first region of the workpiece, wherein the first FET capacitor structure has a first source-gate threshold voltage;
forming a second FET capacitor structure within a second region of the workpiece, wherein the second FET capacitor structure has a second source-gate threshold voltage, different than the first source-gate threshold voltage;
coupling both a source and a drain of the first FET capacitor structure in electrical parallel with a source and a drain of the second FET capacitor structure; and
coupling a gate electrode of the first FET capacitor structure in electrical parallel with a gate electrode of the second FET capacitor structure.

14. The method of claim 13 , wherein forming the first FET capacitor structure and the second FET capacitor structure further comprises:
forming the first source and the first drain coupled through a first channel region comprising the first III-N material;
forming the second source and the second drain coupled through a second channel region the first III-N material;
forming a first recess that exposes a first thickness of III-N material within the first channel region;
forming a second recess that exposes a second thickness of III-N material within the second channel region;
forming a first gate stack within the first recess, the first gate stack comprising the gate electrode separated from the first channel region by a gate dielectric;
forming a second gate stack within the second recess, the second gate stack comprising a gate electrode separated from the second channel region by a gate dielectric; and
forming an interconnect contacting both the first gate electrode and the second gate electrode.

15. The method of claim 14 , wherein:
forming the first recess further comprises:
forming a first mask with a first opening over a first portion of the second III-N material; and
etching partially through the second III-N material within the first opening;

forming the second recess further comprises:
forming a second mask with a second opening over a second portion of the second III-N material; and

etching partially

Assignees

• Intel Corp

Inventors

• Then Han Wui
• Radosavljevic Marko
• Dasgupta Sansaptak
• Fischer Paul
• Hafez Walid
• Mckubre Nicholas

Classifications

• H10D1/66

  Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors · CPC title

• H10D84/811 Primary

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D84/217

  of only conductor-insulator-semiconductor capacitors · CPC title

• H10D84/01

  Manufacture or treatment · CPC title

• H10D84/05

  using Group III-V technology · CPC title