Asymmetric varactor

Patent metadata

Field	Value
Publication number	US-10692862-B2
Application number	US-201815881534-A
Country	US
Kind code	B2
Filing date	Jan 26, 2018
Priority date	Jan 26, 2017
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

An accumulation-mode MOS varactor is formed with a standard CMOS process and having an anti-symmetric-CV curve. The asymmetric varactor (ASVAR) can efficiently generate even-order harmonics while simultaneously suppressing odd-order harmonics over broad bandwidths. This is achieved without degradation of dynamic cut-off frequency. The improved cut-off frequency of the asymmetric varactor results in efficient even-harmonic generation well into sub-millimeter or terahertz frequencies. This and the inherent adaptive-CV features of the asymmetric varactor result in even-harmonic generation with process variation resilience and can also be utilized for frequency response shaping and for optimizing performance at various driving conditions.

First claim

The invention claimed is:

1. A frequency multiplier comprising:
an asymmetric varactor;
the asymmetric varactor comprising:
a first varactor of the asymmetric varactor, and
a second varactor of the asymmetric varactor;

the first varactor of the asymmetric varactor comprising:
a first layer, and
a third layer;

the second varactor of the asymmetric varactor comprising:
a first layer, and,
a third layer;

the first layer of the first varactor of the asymmetric varactor electrically connected to the first layer of the second varactor of the asymmetric varactor and to a first bias signal;
the third layer of the first varactor of the asymmetric varactor connected to a potential;
the third layer of the second varactor of the asymmetric varactor connected to a second bias signal;
in response to the first bias signal, the second bias signal, and an input signal, the asymmetric varactor:
exhibits an adaptive capacitance-voltage characteristic curve comprising a first portion with increasing capacitance that is not responsive to a change in a level of the second bias signal and a second portion that shifts in response to the change in the level of the second bias signal; and,

generates an output signal comprising an output frequency that is an even order multiple of an input frequency of the input signal.

2. The frequency multiplier of claim 1 :
wherein the potential is ground; and,
wherein the output frequency is greater than about 0.3 terahertz.

3. The frequency multiplier of claim 1 , further comprising:
in response to the first bias signal, the second bias signal, and the input signal, the asymmetric varactor:
enhances one or more even order harmonic of the input frequency.

4. The frequency multiplier of claim 1 , further comprising:
in response to the first bias signal, the second bias signal, and the input signal, the asymmetric varactor:
suppresses one or more odd-order harmonics of the input frequency.

5. The frequency multiplier of claim 1 ,
wherein the first varactor of the asymmetric varactor and the second varactor of the asymmetric varactor are metal oxide semiconductor (MOS) devices and are of a same doping type.

6. The frequency multiplier of claim 5 ,
wherein the first varactor of the asymmetric varactor is an n-type varactor and the second varactor of the asymmetric varactor is an n-type varactor.

7. The frequency multiplier of claim 1 ,
wherein the first bias signal is a first bias signal of a second stage,
the second bias signal is a second bias signal of the second stage,
the input signal is a first stage output signal,
the output signal is a second stage output signal, and
the frequency multiplier further comprises:
a first stage;
the second stage;
the first stage comprising a symmetric varactor;
the second stage comprising the asymmetric varactor;
the symmetric varactor comprising:
a first varactor of the symmetric varactor, and
a second varactor of the symmetric varactor;

the first varactor of the symmetric varactor comprising:
a first layer, and
a third layer;

the second varactor of the symmetric varactor comprising:
a first layer, and
a third layer;

the first layer of the first varactor of the symmetric varactor electrically connected to the first layer of the second varactor of the symmetric varactor and to a first bias signal of the first stage;
the third layer of the first varactor of the symmetric varactor connected to a potential;
the third layer of the second varactor of the symmetric varactor connected to a second bias signal of the first stage; and,
in response to the first bias signal of the first stage, the second bias signal of the first stage, and a first stage input signal, the symmetric varactor generates the first stage output signal comprising a first stage output frequency that is an odd order multiple of a first stage input frequency of the first stage input signal.

8. The frequency multiplier of claim 7 :
wherein the potential is ground;
wherein the first stage output frequency is less than about 5 terahertz; and,
wherein a second stage output frequency of the second stage output signal is up to about 10 terahertz.

9. The frequency multiplier of claim 7 , further comprising:
in response to the first bias signal of the first stage, the second bias signal of the first stage, and the first stage input signal, the symmetric varactor:
enhances one or more odd order harmonics of the first stage input signal; and,

in response to the first bias of the second stage signal, the second bias signal of the second stage, and the first stage output signal, the asymmetric varactor:
enhances one or more even order harmonics of the first stage output signal, and
suppresses one or more odd order harmonics of the first stage output signal.

10. The frequency multiplier of claim 7 , further comprising:
wherein the first varactor of the symmetric varactor and the second varactor of the symmetric varactor are metal oxide semiconductor (MOS) devices and are of a different doping type; and,
wherein the first varactor of the asymmetric varactor and the second varactor of the asymmetric varactor are metal oxide semiconductor (MOS) devices and are of a same doping type.

11. The frequency multiplier of claim 7 , further comprising:
wherein the first varactor of the symmetric varactor is a p-type varactor and the second varactor of the symmetric varactor is an n-type varactor; and,
wherein the first varactor of the asymmetric varactor is an n-type varactor and the second varactor of the asymmetric varactor is an n-type varactor.

12. The frequency multiplier of claim 1 wherein the adaptive capacitance-voltage characteristic curve comprises at least three inflection points in which the position of at least one of the three inflection points shifts in response to the change in level of the second bias signal.

13. A frequency multiplier comprising:
an asymmetric varactor;
the asymmetric varactor comprising:
a first varactor of the asymmetric varactor, and
a second varactor of the asymmetric varactor;

the first varactor of the asymmetric varactor comprising:
a first layer, and
a third layer;

the second varactor of the asymmetric varactor comprising:
a first layer, and,
a third layer;

the first layer of the first varactor of the asymmetric varactor electrically connected to the first layer of the second varactor of the asymmetric varactor and to a first bias signal;
the third layer of the first varactor of the asymmetric varactor connected to a potential;
the third layer of the second varactor of the asymmetric varactor connected to a second bias signal;
in response to the first bias signal, the second bias signal, and an input signal, the asymmetric varactor:
exhibits an adaptive capacitance-voltage characteristic curve comprising a first portion with increasing capacitance that is not responsive to a change in the level of the second bias signal and a second portion that shifts in response to the change in level of the second bias signal; and,
generates an output signal comprising an output frequency that is an even order multiple of an input frequency of the input signal;
wherein the third layer of the first varactor and the third layer of the second varactor are of a first doping type; and,
wherein the first bias signal is connected to a well of a second bias type in the third layer.

Assignees

• Univ Texas

Inventors

• Ahmad Zeshan
• O Kenneth K

Classifications

• H10D1/64 Primary

  Variable-capacitance diodes, e.g. varactors · CPC title

• H10D84/215 Primary

  of only varactors · CPC title

• H03K5/00006

  Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68) · CPC title

• H01L29/93

  Electricity · mapped topic

• H01L27/0808 Primary

  Electricity · mapped topic