High breakdown voltage III-N depletion mode MOS capacitors

Patent metadata

Field	Value
Publication number	US-10134727-B2
Application number	US-201514738799-A
Country	US
Kind code	B2
Filing date	Jun 12, 2015
Priority date	Sep 28, 2012
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

First claim

What is claimed is:

1. A III-N metal-oxide-semiconductor (MOS) capacitor, comprising:
a (001) silicon substrate having a trench formed therein with (111) sidewalls and a (001) bottom;
a first dielectric layer on the (001) bottom of the trench;
a GaN layer disposed along at least one of the (111) sidewalls of the trench but not over the first dielectric layer on the (001) bottom of the trench;
a III-N barrier layer disposed on a (0001) surface of the GaN layer; a second dielectric layer disposed over the III-N barrier layer;

a first contact metal disposed on the second dielectric layer; and
a second contact metal disposed on an n-type semiconductor region disposed in contact with the GaN layer and electrically connected to a two dimensional electron gas (2DEG) present in the GaN layer proximate an interface between the GaN layer and the III-N barrier layer.

2. The III-N MOS capacitor of claim 1 , wherein the GaN layer has wurtzite crystallinity.

3. The III-N MOS capacitor of claim 1 , wherein the III-N layer comprises Al-x-yInxGayN.

4. The III-N MOS capacitor of claim 1 , further comprising a third contact disposed on a second n-type semiconductor electrically connected to the 2DEG on a side of the first contact opposite the second contact.

5. The III-N MOS capacitor of claim 4 , wherein the second and third contacts are electrically connected as one voltage node of the capacitor.

6. The III-N MOS capacitor of claim 1 , wherein the first and second contact metals have a work function of 4.6 eV, or lower.

7. The III-N MOS capacitor of claim 1 , wherein the second dielectric layer is a single layer or one in a stack of compositionally distinct layers.

8. The III-N MOS capacitor of claim 1 , wherein the second dielectric layer has a dielectric constant greater than 7.

9. The III-N MOS capacitor of claim 1 , wherein the capacitor has a breakdown voltage exceeding 4V across the first and second contacts.

10. A III-N metal-oxide-semiconductor (MOS) capacitor, comprising:
a (110) silicon substrate having a non-planar silicon body formed therein, the non-planar silicon body having a (111) sidewall;
a GaN layer disposed on the (111) sidewall of the non-planar silicon body;
a III-N barrier layer disposed on a (0001) surface of the GaN layer, wherein the (0001) surface of the GaN layer is a sidewall of a non-planar GaN body formed in the GaN layer;
a dielectric layer disposed over the III-N barrier layer;
a first contact metal disposed on the dielectric layer; and
a second contact metal disposed on an n-type semiconductor region disposed in contact with the GaN layer and electrically connected to a two dimensional electron gas (2DEG) present in the GaN layer proximate an interface between the GaN layer and the III-N barrier layer.

11. The III-N MOS capacitor of claim 10 , wherein the GaN layer has wurtzite crystallinity.

12. The III-N MOS capacitor of claim 10 , wherein the III-N layer comprises Al 1-x-y In x Ga y N.

13. The III-N MOS capacitor of claim 10 , further comprising a third contact disposed on a second n-type semiconductor electrically connected to the 2DEG on a side of the first contact opposite the second contact.

14. The III-N MOS capacitor of claim 13 , wherein the second and third contacts are electrically connected as one voltage node of the capacitor.

15. The III-N MOS capacitor of claim 10 , wherein the first and second contact metals have a work function of 4.6 eV, or lower.

16. The III-N MOS capacitor of claim 10 , wherein the dielectric layer is a single layer.

17. The III-N MOS capacitor of claim 10 , wherein the dielectric layer is one in a stack of compositionally distinct layers.

18. The III-N MOS capacitor of claim 10 , wherein the dielectric layer has a dielectric constant greater than 7.

19. The III-N MOS capacitor of claim 10 , wherein the capacitor has a breakdown voltage exceeding 4V across the first and second contacts.

20. A III-N metal-oxide-semiconductor (MOS) capacitor, comprising:
a (001) silicon substrate having a trench formed therein with (111) sidewalls; a GaN layer disposed the trench of the (001) silicon substrate;
a III-N barrier layer disposed on a (0001) surface of the GaN layer; a dielectric layer disposed over the III-N barrier layer;
a first contact metal disposed on the dielectric layer;
a second contact metal disposed on an n-type semiconductor region disposed in contact with the GaN layer and electrically connected to a two dimensional electron gas (2DEG) present in the GaN layer proximate an interface between the GaN layer and the III-N barrier layer; and a third contact disposed on a second n-type semiconductor electrically connected to the 2DEG on a side of the first contact opposite the second contact, wherein the second and third contacts are electrically connected as one voltage node of the capacitor.

21. A III-N metal-oxide-semiconductor (MOS) capacitor, comprising:
a (001) silicon substrate having a trench formed therein with (111) sidewalls;
a first dielectric layer on a (001) bottom of the trench;
a GaN layer disposed in the trench of the (001) silicon substrate but not over the first dielectric layer on the (001) bottom of the trench;
a III-N barrier layer disposed on a (0001) surface of the GaN layer;
a second dielectric layer disposed over the III-N barrier layer;
a first contact metal disposed on the second dielectric layer; and
a second contact metal disposed on an n-type semiconductor region disposed in contact with the GaN layer and electrically connected to a two dimensional electron gas (2DEG) present in the GaN layer proximate an interface between the GaN layer and the III-N barrier layer, wherein the capacitor has a breakdown voltage exceeding 4V across the first and second contacts.

22. A III-N metal-oxide-semiconductor (MOS) capacitor, comprising:
a (110) silicon substrate having a non-planar silicon body formed therein, the non-planar silicon body having a (111) sidewall;
a GaN layer disposed on the (111) sidewall of the non-planar silicon body; a III-N barrier layer disposed on a (0001) surface of the GaN layer;
a dielectric layer disposed over the III-N barrier layer;
a first contact metal disposed on the dielectric layer;
a second contact metal disposed on an n-type semiconductor region disposed in contact with the GaN layer and electrically connected to a two dimensional electron gas (2DEG) present in the GaN layer proximate an interface between the GaN layer and the III-N barrier layer; and a third contact disposed on a second n-type semiconductor electrically connected to the 2DEG on a side of the first contact opposite the second contact, wherein the second and third contacts are electrically connected as one voltage node of the capacitor.

23. A III-N metal-oxide-semiconductor (MOS) capacitor, comprising: a (110) silicon substrate having a non-planar silicon body formed therein, the non-planar silicon body having a (111) sidewall;
a GaN layer disposed on the (111) sidewall of the non-planar silicon body; a III-N barrier layer disposed on a (0001) surface of the GaN layer;
a dielectric layer disposed over the III-N barrier layer;
a first contact metal disposed on the dielectric layer; and
a second contact metal disposed on an n-type semiconductor region disposed in contact with the GaN layer and electrically connected to a two dimensional electron gas (2DEG) present in the GaN layer proximate an interface between the GaN layer and the III-N ba

Assignees

• Intel Corp

Inventors

• Then Han Wui
• Dasgupta Sansaptak
• Schrom Gerhard
• Rao Valluri R
• Chau Robert S

Classifications

• H01L29/205

  Electricity · mapped topic

• H01L29/1095

  Electricity · mapped topic

• H01L29/2003

  Electricity · mapped topic

• H01L29/045

  Electricity · mapped topic

• H01L21/8258

  Electricity · mapped topic