Methods for forming three-dimensional memory devices with supporting structure for staircase region

Patent metadata

Field	Value
Publication number	US-11380629-B2
Application number	US-202017085406-A
Country	US
Kind code	B2
Filing date	Oct 30, 2020
Priority date	Jul 31, 2020
Publication date	Jul 5, 2022
Grant date	Jul 5, 2022

Abstract

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A peripheral circuit is formed on a first substrate. A first semiconductor layer is formed on a second substrate. A supporting structure and a second semiconductor layer coplanar with the supporting structure are formed on the first semiconductor layer. A memory stack is formed above the supporting structure and the second semiconductor layer. The memory stack has a staircase region overlapping the supporting structure. A channel structure extending vertically through the memory stack and the second semiconductor layer into the first semiconductor layer is formed. The first substrate and the second substrate are bonded in a face-to-face manner.

First claim

What is claimed is:

1. A method for forming a three-dimensional (3D) memory device, comprising:
sequentially forming a first semiconductor layer, a first block layer, and a sacrificial layer on a substrate;
forming a block plug extending vertically through the sacrificial layer and the first block layer to divide the sacrificial layer into a supporting portion and a sacrificial portion;
forming a dielectric stack above the sacrificial layer and having a staircase region, such that the supporting portion of the sacrificial layer is below and overlaps the staircase region of the dielectric stack;
forming a channel structure extending vertically through the dielectric stack, the sacrificial portion of the sacrificial layer, and the first block layer, into the first semiconductor layer;
forming an opening extending vertically through the dielectric stack to expose part of the sacrificial portion of the sacrificial layer; and
replacing, through the opening, the sacrificial portion of the sacrificial layer with a second semiconductor layer coplanar with the supporting portion of the sacrificial layer.

2. The method of claim 1 , wherein replacing the sacrificial portion of the sacrificial layer with the second semiconductor layer comprises:
removing, through the opening, the sacrificial portion of the sacrificial layer to form a cavity, stopping at the block plug and the first block layer; and
depositing, through the opening, doped polysilicon into the cavity to form the second semiconductor layer.

3. The method of claim 2 , wherein forming the channel structure comprises:
forming a channel hole extending vertically through the dielectric stack, the sacrificial portion of the sacrificial layer, and the first block layer, into the first semiconductor layer; and
sequentially forming a memory film and a semiconductor channel along a sidewall of the channel hole.

4. The method of claim 3 , wherein replacing the sacrificial portion of the sacrificial layer with the second semiconductor layer further comprises removing, through the opening, part of the memory film to expose part of the semiconductor channel along the sidewall of the channel hole, such that the second semiconductor layer is in contact with the exposed part of the semiconductor channel.

5. The method of claim 1 , wherein forming the block plug comprises:
forming a dent extending vertically through the sacrificial layer and the first block layer; and
depositing silicon oxide to fill the dent and be connected to the first block layer.

6. The method of claim 1 , further comprising:
after forming the sacrificial layer, forming a second block layer on the sacrificial layer, such that the block plug extends vertically through the second block layer as well; and
forming a third semiconductor layer on the second block layer and the block plug.

7. The method of claim 1 , wherein the sacrificial layer comprises polysilicon or silicon nitride.

8. The method of claim 1 , further comprising, after replacing the sacrificial portion of the sacrificial layer with the second semiconductor layer, replacing, through the opening, the dielectric stack with a memory stack.

9. A method for forming a three-dimensional (3D) memory device, comprising:
sequentially forming a first semiconductor layer, a first block layer, and a sacrificial layer on a substrate;
replacing part of the first block layer and the sacrificial layer with a supporting structure;
forming a dielectric stack above the supporting structure and a remainder of the sacrificial layer and having a staircase region, such that the supporting structure overlaps the staircase region of the dielectric stack;
forming a channel structure extending vertically through the dielectric stack, the remainder of the sacrificial layer, and the first block layer, into the first semiconductor layer;
forming an opening extending vertically through the dielectric stack to expose part of the remainder of the sacrificial layer; and
replacing, through the opening, the remainder of the sacrificial layer with a second semiconductor layer coplanar with the supporting structure.

10. The method of claim 9 , wherein replacing the remainder of the sacrificial layer with the second semiconductor layer comprises:
removing, through the opening, the remainder of the sacrificial layer to form a cavity; and
depositing, through the opening, doped polysilicon into the cavity to form the second semiconductor layer.

11. The method of claim 9 , wherein replacing the part of the first block layer and the sacrificial layer with the supporting structure comprises:
removing the part of the first block layer and the sacrificial layer to form a trench; and
depositing silicon oxide to fill the trench.

12. The method of claim 9 , further comprising:
after forming the sacrificial layer, forming a second block layer on the sacrificial layer, such that a top surface of the second block layer is flush with a top surface of the supporting structure; and
forming a third semiconductor layer on the second block layer and the supporting structure.

13. The method of claim 9 , further comprising after replacing the part of the first block layer and the sacrificial layer with the supporting structure, replacing, through the opening, the dielectric stack with a memory stack.

14. A method for forming a three-dimensional (3D) memory device, comprising:
forming a peripheral circuit on a first substrate;
forming a first semiconductor layer on a second substrate;
forming a supporting structure and a second semiconductor layer coplanar with the supporting structure on the first semiconductor layer;
forming a memory stack above the supporting structure and the second semiconductor layer, the memory stack having a staircase region overlapping the supporting structure;
forming a channel structure extending vertically through the memory stack and the second semiconductor layer into the first semiconductor layer; and
bonding the first substrate and the second substrate in a face-to-face manner.

15. The method of claim 14 , wherein forming the supporting structure and the second semiconductor layer comprises:
forming a block layer on the first semiconductor layer and a sacrificial layer on the block layer;
forming a block plug extending vertically through the sacrificial layer and the block layer to divide the sacrificial layer into a supporting portion and a sacrificial portion; and
replacing the sacrificial portion of the sacrificial layer with the second semiconductor layer.

16. The method of claim 14 , wherein forming the supporting structure and the second semiconductor layer comprises:
forming a block layer on the first semiconductor layer and a sacrificial layer on the block layer;
replacing part of the block layer and the sacrificial layer with the supporting structure; and
replacing a remainder of the sacrificial layer with the second semiconductor layer.

17. The method of claim 14 , further comprising, after bonding:
thinning the second substrate to expose the first semiconductor layer; and
forming a source contact above and in contact with the first semiconductor layer.

18. The method of claim 14 , further comprising, prior to bonding, forming a source contact above and in contact with the first semiconductor layer.

19. The method of claim 14 , wherein, after bonding, the memory stack is above the peripheral circuit, the method further comprising:
thinning the second substrate to expose the first semiconductor layer; and
forming a contact th

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhang Kun
• Wu Linchun
• Zhang Zhong
• Zhou Wenxi
• Huo Zongliang

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title