Three-dimensional semiconductor memory device including an electrode connecting portion

Patent metadata

Field	Value
Publication number	US-11374019-B2
Application number	US-202016837169-A
Country	US
Kind code	B2
Filing date	Apr 1, 2020
Priority date	Jan 18, 2016
Publication date	Jun 28, 2022
Grant date	Jun 28, 2022

Abstract

A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.

First claim

What is claimed is:

1. A three-dimensional semiconductor memory device, comprising:
a substrate including a cell array region and a connection region; and
first and second electrode structures, each comprising first and second electrodes alternatingly and vertically stacked on the substrate,
wherein, in each of the first and second electrode structures, each of the first and second electrodes comprises:
a plurality of electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction;
an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other; and
at least one protrusion provided on the connection region to extend from the electrode connecting portion in the first direction,
wherein each of the first and second electrode structures has a first stair-step structure extending in the first direction and a second stair-step structure extending in the first direction on the connection region,
wherein the protrusions of the first electrodes exposed by the second electrodes serve as first pad regions defining the first stair-step structure, and the protrusions of the second electrodes exposed by the first electrodes serve as second pad regions defining the second stair-step structure,
wherein the second stair-step structure is adjacent to the first stair-step structure in the second direction, and
wherein the electrode connecting portion of each of the first and second electrodes of the first electrode structure is electrically separated from the electrode connecting portion of each of the first and second electrodes of the second electrode structure.

2. The device of claim 1 , wherein the first electrode structure is disposed to be spaced apart from the second electrode structure in the second direction, and
the first stair-step structure of the first electrode structure is adjacent to the first stair-step structure of the second electrode structure in the second direction.

3. The device of claim 1 , wherein each of the first and second stair-step structures has a thickness decreasing in a stepwise manner in the first direction.

4. The device of claim 1 , wherein the protrusions of each of the second electrodes comprises a first protrusion, which is extended from the electrode connecting portion by a first length in the first direction, and a second protrusion, which is extended from the electrode connecting portion by a second length smaller than the first length.

5. The device of claim 4 , wherein the first protrusions of the second electrodes have side surfaces aligned to those of the protrusions of the first electrodes positioned therebelow.

6. The device of claim 1 , further comprising:
first contact plugs coupled to the first pad regions, respectively; and
second contact plugs coupled to the second pad regions, respectively.

7. The device of claim 6 , wherein each of the electrode portions has a first width in the second direction, and
a distance between the first and second contact plugs adjacent to each other in the second direction is greater than the first width.

8. The device of claim 6 , wherein the connection region comprises first and second connection regions spaced apart from each other with the cell array region interposed therebetween,
the first and second stair-step structures of the first and second electrode structures are provided on the first and second connection regions, respectively,
the first contact plugs connected to the first electrodes of the first and second electrode structures are provided on the first connection region, and
the second contact plugs connected to the second electrodes of the first and second electrode structures are provided on the second connection region.

9. The device of claim 6 , wherein the connection region comprises first and second connection regions spaced apart from each other with the cell array region interposed therebetween,
the first and second stair-step structures of the first and second electrode structures are provided on the first and second connection regions, respectively,
the first and second contact plugs coupled to the first and second electrodes of the first electrode structure are provided on the first connection region,
the first and second contact plugs coupled to the first and second electrodes of the second electrode structure are provided on the second connection region.

10. The device of claim 6 , further comprising,
first interconnection lines coupled to the first contact plugs, respectively; and
second interconnection lines coupled to the second contact plugs, respectively,
wherein the first interconnection lines and the second interconnection lines are located at the same vertical level from the substrate.

11. The device of claim 10 , wherein the first interconnection lines electrically connected to the first electrodes of the first electrode structure are electrically separated from the first and second electrodes of the second electrode structure.

12. A three-dimensional semiconductor memory device comprising:
a substrate including a cell array region and a connection region; and
first and second electrode structures, each comprising first and second electrodes alternatingly and vertically stacked on the substrate,
wherein each of the first and second electrodes of the first and second electrode structures comprises:
a plurality of electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction;
an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other; and
at least one protrusion provided on the connection region to extend from the electrode connecting portion in the first direction,
wherein each of the first and second electrode structures has a first stair-step structure and a second stair-step structure on the connection region,
wherein the protrusions of the first electrodes exposed by the second electrodes serve as first pad regions defining the first stair-step structure, and the protrusions of the second electrodes exposed by the first electrodes serve as second pad regions defining the second stair-step structure,
wherein the second stair-step structure is adjacent to the first stair-step structure in the second direction, and
wherein the protrusions of each of the first electrodes comprises a first protrusion, which is exposed by the second electrodes positioned thereon, and a second protrusion, which is overlapped with the protrusions of the second electrodes when viewed in a plan view.

13. A three-dimensional semiconductor memory device, comprising:
a substrate including a cell array region and a connection region;
an electrode structure comprising first and second electrodes alternatingly and vertically stacked on the substrate, each of the first electrodes having a first pad region and each of the second electrodes having a second pad region,
first contact plugs coupled to the first pad regions of the first electrodes, respectively;
second contact plugs coupled to the second pad regions of the second electrodes, respectively;
first interconnection lines coupled to the first contact plugs, respectively; and
second interconnection lines coupled to the second contact plugs, respectively,
wherein the electrode structure has a stair-step structure on the connection region,
whe

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Chang-Sup
• Lee Sung-Hun
• Lee Joonhee
• Cho Seong Soon

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D30/6892

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title

• H10D30/696

  having at least one additional gate, e.g. program gate, erase gate or select gate · CPC title