Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9711603-B2
Application number	US-201514956735-A
Country	US
Kind code	B2
Filing date	Dec 2, 2015
Priority date	Dec 10, 2014
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the conductive pattern, forming a contact hole in the filling insulation layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole such that the opening is connected to the contact hole, and forming a contact plug filling the contact hole and the opening. A width of the opening is greater than a width of the contact hole.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
first and second conductive patterns stacked on the substrate, each of the first and second conductive patterns extending in a first direction, the second conductive pattern have a length less than the first conductive pattern in the first direction;
a filling insulation layer covering the first and second conductive patterns; and
first and second contact plugs on the substrate,
the first contact plug including a first contact plate in the first conductive pattern and a first contact body on a top surface of the first contact plate and penetrating the filling insulation layer,

a width of the top surface of the first contact plate being greater than a width of a bottom surface of the first contact body,
the second contact plug including a second contact plate in the second conductive pattern and a second contact body on a top surface of the second contact plate and penetrating the filling insulating layer,
a width of the top surface of the second contact plate being greater than a width of a bottom surface of the second contact body.

2. The semiconductor device of claim 1 , wherein the first contact plate has a circular plate structure.

3. The semiconductor device of claim 1 , wherein a material of the first contact plate is the same as a material of the first contact body.

4. The semiconductor device of claim 1 , wherein the first contact plate penetrates the first conductive pattern.

5. A method for manufacturing a semiconductor device, the method comprising:
forming first and second conductive patterns stacked on a substrate, each of the first and second conductive patterns extending in a first direction, the second conductive pattern having a length less than the first conductive pattern in the first direction;
forming a filling insulation layer covering the first and second conductive patterns;
forming first and second contact holes in the filling insulation layer, a bottom of the first contact hole being adjacent to the first conductive pattern, a bottom of the second contact hole being adjacent to the second conductive pattern;
forming a first opening in the first conductive pattern by partially removing the first conductive pattern and a second opening in the second conductive pattern by partially removing the second conductive pattern, the first opening being connected to the first contact hole, the second opening being connected to the second contact hole; and
forming a first contact plug filling the first contact hole and the first opening and a second contact plug filling in the second contact hole and the second opening,
wherein a width of the first opening is greater than a width of the first contact hole and
wherein a width of the second opening is greater than a width of the second contact hole.

6. The method of claim 5 , further comprising:
forming a barrier layer conformally covering inner surfaces of the first and second contact holes and the first and second opening before the forming the first and second contact plugs.

7. The method of claim 5 , wherein the first opening extends from a top surface to a bottom surface of the first conductive pattern.

8. The method of claim 5 , wherein the forming the second contact hole includes exposing the second conductive pattern through the first contact hole.

9. The method of claim 5 , wherein the forming the first and second openings is performed using a wet etching process.

10. The method of claim 9 , wherein an etch rate of the first conductive pattern is higher than an etch rate of the filling insulation layer during the wet etching process.

11. The method of claim 9 , wherein the forming the first and second contact holes is performed using a dry etching process filling.

12. The method of claim 9 , wherein
the forming the first contact hole includes leaving a residue of the filling insulation layer between the first conductive pattern and the bottom of the first contact hole,
the forming the second contact hole includes exposing the second conductive pattern through the second contact hole, and
the forming the first and second openings includes removing the residue during the wet etching process.

13. A semiconductor device comprising:
a stack structure on a substrate,
the stack structure including a plurality of electrodes sequentially stacked on the substrate,
each of the plurality of electrodes including an end portion,
the end portions of the plurality of electrodes defining a stepwise structure;

an insulating layer covers the stepwise structure; and
a plurality of contact plugs being plugged in the end portions of the plurality of electrodes respectively, each of the plurality of contact plugs penetrating the insulating layer,
wherein at least one of the plurality of contact plugs includes a contact plate in the end portion of a corresponding one of the plurality of electrodes and a contact body on the contact plate and penetrating the insulation layer, and
wherein a width of the contact plate is greater than a width of the contact body.

14. The semiconductor device of claim 13 , wherein the contact plate penetrates the end portion of the corresponding one of the plurality of electrodes.

15. The semiconductor device of claim 13 , wherein a bottom surface of the contact plate is substantially parallel with a top surface of the substrate.

16. The semiconductor device of claim 13 , further comprises a plurality of vertical channel structures on the substrate,
wherein each of the plurality of vertical channel structures penetrates the plurality of electrodes.

17. The semiconductor device of claim 1 , wherein a bottom surface of the first contact plate is substantially parallel with a top surface of the substrate, and
wherein a bottom surface of the second contact plate is substantially parallel with the top surface of the substrate.

18. The semiconductor device of claim 1 , further comprises a vertical channel structure on the substrate, the vertical channel structure penetrating the first and second conductive patterns.

19. The semiconductor device of claim 1 , wherein the width of the top surface of the second contact plate is larger than the width of the top surface of the first contact plate.

20. The method of claim 5 , wherein the second width of the second opening is larger than the first width of the first opening.

Assignees

• Lim Tae-Wan
• Kang Hojong
• Park Joowon
• Samsung Electronics Co Ltd

Inventors

• Lim Tae-Wan
• Kang Hojong
• Park Joowon

Classifications

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/40 Primary

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title