Vertical type semiconductor devices

Patent metadata

Field	Value
Publication number	US-9306041-B2
Application number	US-201414156607-A
Country	US
Kind code	B2
Filing date	Jan 16, 2014
Priority date	Jan 17, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A vertical type semiconductor device includes first and second word line structures that include first and second word lines. The word lines surround a plurality of pillar structures, which are provided to connect the word lines to corresponding string select lines. Connecting patterns electrically connect pairs of adjacent first and second word lines in a same plane. The device may be a nonvolatile memory device or a different type of device.

First claim

What is claimed is:

1. A vertical type semiconductor device, comprising:
a plurality of pillar structures extending in a first direction, the pillar structures including channel patterns and being arranged in a second direction and a third direction crossing the second direction;
a first word line structure surrounding the pillar structures, the first word line structure extending in the second direction and including first word lines, the first word lines being spaced apart from each other and stacked in the first direction;
a second word line structure surrounding the pillar structures, the second word line structure extending in the second direction and including second word lines, the second word lines being spaced apart from each other and stacked in the first direction, the second word line structure being disposed adjacent to the first word line structure in the third direction;
a plurality of connecting patterns to connect side walls of adjacent first and second word lines, the connecting patterns being electrically coupled with the first and second word lines positioned at a same level; and
a plurality of string select lines coupled to string select transistors on the first and second word line structures, each of the string select lines surrounding at least one pillar structure in the third direction and extending in the second direction, the string select lines separated from the first and second word line structures.

2. The device as claimed in claim 1 , wherein:
the first and second word lines and the connecting patterns are positioned at the same level correspond to word line patterns, and
the word line pattern in one layer is connected with one contact plug and one connecting wiring electrically coupled to the contact plug.

3. The device as claimed in claim 2 , wherein the word line patterns are arranged in a block unit and wherein the first and second word lines positioned in a block region of the block unit are electrically connected.

4. The device as claimed in claim 1 , wherein the connecting patterns at each layer are arranged in the third direction.

5. The device as claimed in claim 1 , further comprising a ground select transistor including a ground select line, wherein the ground select line is under the first and second word lines at a lowest layer.

6. The device as claimed in claim 1 , wherein the first and second word lines extend to surround at least one pillar structure in the third direction.

7. The device as claimed in claim 1 , wherein the first and second word lines are wider than the string select line.

8. The device as claimed in claim 1 , wherein the first and second word lines have substantially a same line width as the string select line.

9. The device as claimed in claim 1 , wherein the connecting pattern includes a same conductive material as the first and second word lines.

10. The device as claimed in claim 9 , wherein the conductive material comprises a barrier metal material including a metal nitride and a metal material including tungsten.

11. The device as claimed in claim 1 , wherein:
a portion of the string select line facing the connecting pattern in the first direction is wider than another portion of the string select line.

12. The device as claimed in claim 1 , further comprising a plurality of stacked layer structures, wherein each stacked layer structure includes a tunnel insulating layer pattern, a charge storing layer pattern, and a blocking layer pattern arranged on a side wall of a corresponding one of the pillar structures.

13. A vertical type semiconductor device, comprising:
a plurality of pillar structures extending in a first direction, the pillar structures including a channel pattern and being arranged in a second direction and a third direction crossing the second direction;
a word line pattern including word lines and connecting patterns, the word lines surrounding the pillar structures, extending in the second direction, and being repeatedly arranged in parallel in the third direction, the connecting patterns connecting side walls of the word lines to electrically connect the word lines repeatedly arranged in parallel to each other in the third direction; and
a plurality of string select lines coupled to respective string select transistors, each of the string select lines extending in a second direction and provided higher than an uppermost word line pattern and surrounding one pillar structure in the third direction, the string select lines separated from the word line pattern.

14. The device as claimed in claim 13 , wherein a plurality of the word line patterns are stacked and spaced apart from each other in the first direction.

15. The device as claimed in claim 14 , wherein one word line pattern of one layer is provided with one contact plug and a connecting wiring electrically coupled to the contact plug.

16. A vertical type semiconductor device, comprising:
a first word line;
a second word line;
a connector to electrically connect the first word line and the second word line to form a word line pattern;
at least one string select line over the word line pattern; and
a number of pillars passing through the at least one string select line and the first and second word lines of the word line pattern, wherein the connector is substantially coplanar with the first and second word lines and is located at an area different from adjacent ends of the first and second word lines.

17. The device as claimed in claim 16 , wherein at least two pillars pass through the first word line and at least two pillars pass through the second word line.

18. The device as claimed in claim 16 , wherein the connector is to connect side walls of the first and second word lines.

19. The device as claimed in claim 16 , further comprising:
a plurality of the word line patterns in a stacked arrangement,
wherein ends of the stacked word line patterns are stepped in a predetermined direction.

20. The device as claimed in claim 16 , wherein widths of each of the first word line and the second word line are different from a width of the string select line.

Assignees

• Hwang Sung-Min
• Kim Han-Soo
• Lee Woon-Kyung
• Cho Won-Seok
• Samsung Electronics Co Ltd

Inventors

• Hwang Sung-Min
• Kim Han-Soo
• Lee Woon-Kyung
• Cho Won-Seok

Classifications

• H10D84/016

  the components including vertical IGFETs · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D30/0413 Primary

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H01L27/11575

  Electricity · mapped topic

• H01L29/66833 Primary

  Electricity · mapped topic