Systems and methods for improving within die co-planarity uniformity

Patent metadata

Field	Value
Publication number	US-11367653-B2
Application number	US-201916572920-A
Country	US
Kind code	B2
Filing date	Sep 17, 2019
Priority date	Sep 20, 2018
Publication date	Jun 21, 2022
Grant date	Jun 21, 2022

Abstract

Exemplary methods of producing a semiconductor substrate may include characterizing a substrate pattern to identify a zonal distribution of a plurality of vias and a height and a radius of each via of the plurality of vias. The methods may include determining a fill rate for each via within the zonal distribution of the plurality of vias. The methods may include modifying a die pattern to adjust via fill rates between two zones of vias. The methods may also include producing a substrate according to the die pattern.

First claim

What is claimed is:

1. A method of producing a semiconductor substrate, the method comprising:
characterizing a substrate pattern to identify a zonal distribution of a plurality of vias and a height and a radius of each via of the plurality of vias;
determining a fill rate for each via within the zonal distribution of the plurality of vias;
modifying a die pattern to adjust via fill rates between two zones of vias;
producing a substrate according to the die pattern; and
filling vias on the substrate with a first metal followed by a second metal, wherein the vias are filled to a height where an average fill height of the second metal is less than or about twice an average via radius of the plurality of vias.

2. The method of producing a semiconductor substrate of claim 1 , wherein the modifying comprises increasing or decreasing via radius on one zone of the two zones of vias on the die pattern.

3. The method of producing a semiconductor substrate of claim 1 , wherein the modifying comprises increasing or decreasing a percentage open area in one zone of the two zones of vias on the die pattern.

4. The method of producing a semiconductor substrate of claim 1 , wherein the second metal is characterized by a melting temperature below a melting temperature of the first metal.

5. The method of producing a semiconductor substrate of claim 4 , further comprising performing a reflow operation of the second metal to produce an arcuate shape for the second metal within each via.

6. The method of producing a semiconductor substrate of claim 5 , wherein, subsequent the reflow operation, at least one via characterized by a pre-flow fill height of the second metal greater than the average fill height of the second metal is characterized by a post-reflow fill height less than the pre-flow fill height of the second metal.

7. The method of producing a semiconductor substrate of claim 5 , wherein, subsequent the reflow operation, at least one via characterized by a pre-flow fill height of the second metal less than the average fill height of the second metal is characterized by a post-reflow fill height greater than the pre-flow fill height of the second metal.

Assignees

• Applied Materials Inc

Inventors

• Mchugh Paul
• Roh Kwan Wook
• Wilson Gregory J

Classifications

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/089 Primary

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056 Primary

  by filling conductive material into holes, grooves or trenches · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title