Semiconductor devices including thick pad

Patent metadata

Field	Value
Publication number	US-11355467-B2
Application number	US-202016983296-A
Country	US
Kind code	B2
Filing date	Aug 3, 2020
Priority date	Jan 15, 2020
Publication date	Jun 7, 2022
Grant date	Jun 7, 2022

Abstract

A semiconductor device may include a semiconductor chip in an encapsulant. A first insulation layer may be disposed on the encapsulant and the semiconductor chip. A horizontal wiring and a primary pad may be disposed on the first insulation layer. A secondary pad may be disposed on the primary pad. A second insulation layer covering the horizontal wiring may be disposed on the first insulation layer. A solder ball may be disposed on the primary pad and the secondary pad. The primary pad may have substantially the same thickness as a thickness of the horizontal wiring.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor chip in an encapsulant;
a first insulation layer on the encapsulant and the semiconductor chip;
a horizontal wiring and a primary pad on the first insulation layer, a thickness of the primary pad substantially the same as a thickness of the horizontal wiring;
a secondary pad on an upper surface of the primary pad;
a second insulation layer on the first insulation layer, the second insulation layer covering the horizontal wiring; and
a solder ball on the primary pad and the secondary pad,
wherein an uppermost surface of the second insulation layer is farther from an upper surface of the first insulation layer than a top surface of the secondary pad, and
the upper surface of the primary pad is above a lowermost surface of the second insulating layer.

2. The semiconductor device of claim 1 , wherein a width at an upper surface the secondary pad is greater than a width at a lower surface of the secondary pad.

3. The semiconductor device of claim 1 , wherein the secondary pad has a width which is narrower than a width of the primary pad.

4. The semiconductor device of claim 1 , wherein the secondary pad comprises the same material as a material of the primary pad.

5. The semiconductor device of claim 1 , wherein the secondary pad and the primary pad comprise a copper (Cu) layer.

6. The semiconductor device of claim 1 , wherein the secondary pad comprises at least one of a bar shape, a ring shape, a plurality of pillar shapes, a plurality of embossing shapes, an amoebic shape.

7. The semiconductor device of claim 1 , wherein the primary pad comprises the same material layer as the horizontal wiring.

8. The semiconductor device of claim 1 , wherein a side surface of the primary pad has substantially the same profile as a profile of a side surface of the horizontal wiring when viewed in a cross-section view.

9. The semiconductor device of claim 1 , wherein a width at the upper surface of the primary pad is greater than a width at a lower surface of the primary pad.

10. The semiconductor device of claim 1 , wherein
the second insulation layer covers an edge of the primary pad, and
the solder ball extends to an inner portion of the second insulation layer, contacts a top surface of the primary pad, and contacts a top surface and a side surface of the secondary pad.

11. The semiconductor device of claim 1 , further comprising:
a first seed layer,
wherein the primary pad is between the first seed layer and the secondary pad.

12. The semiconductor device of claim 11 , further comprising:
a first undercut region between the primary pad and the first insulation layer,
wherein the second insulation layer extends to an inner portion of the first undercut region and contacts a bottom surface of the primary pad and a side surface of the first seed layer.

13. The semiconductor device of claim 11 , further comprising:
a second seed layer between the primary pad and the secondary pad.

14. The semiconductor device of claim 13 , further comprising:
a second undercut region between the secondary pad and the primary pad,
wherein the solder ball extends to an inner portion of the second undercut region and contacts a bottom surface of the secondary pad and a side surface of the second seed layer.

15. The semiconductor device of claim 1 , further comprising:
a chip pad in the semiconductor chip,
a contact plug in an inner portion of the first insulation layer, the contact plug electrically connected to the chip pad, and
the horizontal wiring is disposed on the contact plug.

16. The semiconductor device of claim 1 , further comprising:
a chip pad in the semiconductor chip; and
a contact plug in an inner portion of the first insulation layer, the contact plug electrically connected to the chip pad,
wherein the primary pad is on the contact plug.

17. A semiconductor device comprising:
a semiconductor chip in a package substrate;
a first insulation layer on the package substrate and the semiconductor chip;
a horizontal wiring and a primary pad on the first insulation layer, a thickness of the primary pad substantially the same as a thickness of the horizontal wiring;
a secondary pad on the primary pad;
a second insulation layer covering the horizontal wiring on the first insulation layer; and
a solder ball on the primary pad and the secondary pad
wherein an uppermost surface of the second insulation layer is farther from an upper surface of the first insulation layer than a top surface of the secondary pad, and
the upper surface of the primary pad is above a lowermost surface of the second insulating layer.

18. The semiconductor device of claim 17 , further comprising an encapsulant between the package substrate and the semiconductor chip.

19. The semiconductor device of claim 17 , further comprising:
a bottom connection terminal, a top connection terminal, and an internal wiring between the bottom connection terminal and the top connection terminal in the package substrate; and
a contact plug in an inner portion of the first insulation layer, the contact plug electrically connected to the top connection terminal to extend to,
wherein the primary pad is disposed on the contact plug.

20. A semiconductor device comprising:
a stack of semiconductor packages, the stack including a plurality of semiconductor packages, wherein each of the plurality of semiconductor packages includes
a semiconductor chip in a package substrate;
a first insulation layer on the package substrate and the semiconductor chip;
a horizontal wiring and a primary pad on the first insulation layer, a thickness of the primary pad substantially the same as a thickness of the horizontal wiring;
a secondary pad on the primary pad;
a second insulation layer covering the horizontal wiring on the first insulation layer; and
a solder ball on the primary pad and the secondary pad,
wherein an uppermost surface of the second insulation layer is farther from an upper surface of the first insulation layer than a top surface of the secondary pad, and
the upper surface of the primary pad is above a lowermost surface of the second insulating layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ko Taeho
• Lee Daehee
• Jung Hyunchul

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10W72/01935

  by plating, e.g. electroless plating or electroplating · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/934

  Cross-sectional shape, i.e. in side view · CPC title