Device, method and system for providing recessed interconnect structures of a substrate

Patent metadata

Field	Value
Publication number	US-11355427-B2
Application number	US-201616095916-A
Country	US
Kind code	B2
Filing date	Jul 1, 2016
Priority date	Jul 1, 2016
Publication date	Jun 7, 2022
Grant date	Jun 7, 2022

Abstract

Techniques and mechanisms to facilitate connectivity between circuit components via a substrate. In an embodiment, a microelectronic device includes a substrate, wherein a recess region extends from the first side of the substrate and only partially toward a second side of the substrate. First input/output (IO) contacts of a first hardware interface are disposed in the recess region. The first IO contacts are variously coupled to each to a respective metallization layer of the substrate, wherein the recess region extends though one or more other metallization layers of the substrate. In another embodiment, the microelectronic device further comprises second IO contacts of a second hardware interface, the second IO contacts to couple the microelectronic device to a printed circuit board.

First claim

What is claimed is:

1. A microelectronic device comprising:
one or more integrated circuit (IC) die;
a substrate coupled to the one or more IC die, wherein sidewalls of the substrate define at least in part a first recess structure which extends from a first side of the substrate and only partially toward a second side of the substrate opposite the first side, wherein first input/output (IO) contacts of a first hardware interface are disposed at a bottom portion of the first recess structure, the first IO contacts coupled to the one or more IC die, wherein the first recess structure extends through one or more metallization layers of the substrate, wherein other sidewalls of the substrate define at least in part a second recess structure which extends from the second side of the substrate and only partially toward the first side of the substrate, wherein the first recess structure has a first lateral width and a first footprint, the second recess structure has a second lateral width and a second footprint, and wherein the first lateral width is greater than the second lateral width, and the second footprint is entirely within the first footprint;
a first circuit component coupled to the substrate, wherein the first circuit component is disposed at least in part in the second recess structure; and
a second hardware interface comprising second IO contacts disposed on the substrate, the second IO contacts to couple the microelectronic device to another device.

2. The microelectronic device of claim 1 , wherein the second hardware interface is disposed on the first side.

3. The microelectronic device of claim 1 , wherein the substrate includes an interposer.

4. The microelectronic device of claim 1 , wherein the first circuit component includes a capacitor.

5. The microelectronic device of claim 1 , wherein the first circuit component includes another IC die.

6. The microelectronic device of claim 1 , wherein the first circuit component includes a packaged device.

7. The microelectronic device of claim 1 , further comprising a package material disposed on the one or more IC die.

8. The microelectronic device of claim 1 , wherein the sidewalls comprise a first sidewall which extends to a first exterior side of the substrate.

9. The microelectronic device of claim 8 , wherein the sidewalls further comprise a second sidewall which extends to a second exterior side of the substrate.

10. The microelectronic device of claim 1 , further comprising a printed circuit board coupled to the substrate via the second hardware interface.

11. A method comprising:
forming in a substrate a first recess structure which extends from a first side of the substrate and only partially through the substrate, wherein the first recess structure extends through one or more metallization layers of the substrate, and wherein the first recess structure has a first lateral width and a first footprint;
forming in the substrate a second recess structure which extends from a second side of the substrate and only partially through the substrate, the second side opposite the first side, wherein the second recess structure extends through one or more metallization layers of the substrate, wherein second recess structure has a second lateral width and a second footprint, and wherein the first lateral width is greater than the second lateral width, and the second footprint is entirely within the first footprint;
forming first input/output (IO) contacts of a first hardware interface at a bottom portion of the first recess structure;
coupling one or more integrated circuit (IC) die to the substrate, wherein the first IO contacts are coupled to the one or more IC die;
coupling a first circuit component coupled to the substrate, wherein the first circuit component is disposed at least in part in the second recess structure; and
disposing on the substrate a second hardware interface comprising second IO contacts.

12. The method of claim 11 , wherein the second hardware interface is disposed on the first side.

13. The method of claim 11 , wherein forming the first recess structure includes laser etching a portion of the substrate.

14. The method of claim 11 , wherein forming the first recess structure includes drilling a portion of the substrate.

15. The method of claim 11 , wherein the substrate includes an interposer.

16. The method of claim 11 , wherein the first recess structure comprises a sidewall which extends to an exterior side of the substrate.

17. A system comprising:
a printed circuit board (PCB);
a microelectronic device coupled to the PCB, the microelectronic device including:
one or more integrated circuit (IC) die;
a substrate coupled to the one or more IC die, wherein sidewalls of the substrate define at least in part a first recess structure which extends from a first side of the substrate and only partially toward a second side of the substrate opposite the first side, wherein first input/output (IO) contacts of a first hardware interface are disposed at a bottom portion of the first recess structure, the first IO contacts coupled to the one or more IC die, wherein the first recess structure extends through one or more metallization layers of the substrate, wherein other sidewalls of the substrate define at least in part a second recess structure which extends from the second side of the substrate and only partially toward the first side of the substrate, wherein the first recess structure has a first lateral width and a first footprint, the second recess structure has a second lateral width and a second footprint, and wherein the first lateral width is greater than the second lateral width, and the second footprint is entirely within the first footprint;

a first circuit component coupled to the substrate, wherein the first circuit component is disposed at least in part in the second recess structure; and
a second hardware interface comprising second IO contacts disposed on the substrate, wherein the PCB is coupled to the microelectronic device via the second IO contacts.

18. The system of claim 17 , wherein the second hardware interface is disposed on the first side.

19. The system of claim 17 , wherein the substrate includes an interposer.

Assignees

• Intel Corp

Inventors

• Loo Howe Yin
• Sharan Sujit
• Chuah Tin Poay
• Prabhakumar Ananth

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title

• H10W70/698

  Semiconductor materials that are electrically insulating, e.g. undoped silicon · CPC title

• H10W70/095

  of vias therein · CPC title