Detection of illegal commands

Patent metadata

Field	Value
Publication number	US-11354064-B2
Application number	US-201916719891-A
Country	US
Kind code	B2
Filing date	Dec 18, 2019
Priority date	Dec 26, 2018
Publication date	Jun 7, 2022
Grant date	Jun 7, 2022

Abstract

Methods, systems, and devices for detection of illegal commands are described. A memory device, such as a dynamic random access memory (DRAM), may receive a command from a device, such as a host device, to perform an access operation on at least one memory cell of a memory device. The memory device may determine, using a detection component, that a timing threshold associated with an operation of the memory device would be violated by performing the access operation. The memory device may refrain from executing the access operation based on determining that performing the access operation included in the command would violate the timing threshold. The memory device may transmit, to the device, an indication that performing the command would violate the timing threshold.

First claim

What is claimed is:

1. A method, comprising:
receiving, from a host device, a command to perform an access operation on a memory cell of a memory device;
determining a type of the received command, from a plurality of types of commands, based at least in part on receiving the command from the host device;
determining, using a detection component of the memory device, that a timing threshold associated with an operation of the memory device would be violated by performing the access operation, wherein the timing threshold is based at least in part on the type of command received from the host device;
transmitting, to the host device, an indication that performing the command by the memory device would violate the timing threshold based at least in part on determining that the timing threshold would be violated; and
locking a bank associated with the memory cell to prevent additional operations being performed on the bank based at least in part on determining that the timing threshold would be violated, wherein the indication transmitted to the host device indicates that the bank is locked.

2. The method of claim 1 , further comprising:
refraining from executing the access operation based at least in part on determining that the timing threshold would be violated using the detection component, wherein transmitting the indication is based at least in part on refraining from executing the access operation.

3. The method of claim 1 , further comprising:
identifying the command received from the host device after receiving the command; and
selecting the timing threshold from a set of timing thresholds based at least in part on the command, wherein determining whether the timing threshold would be violated is based at least in part on selecting the timing threshold.

4. The method of claim 3 , wherein selecting the timing threshold comprises:
selecting a plurality of timing thresholds from the set of timing thresholds based at least in part on the command, wherein determining whether the timing threshold would be violated comprises determining whether at least one of the plurality of timing thresholds would be violated.

5. The method of claim 1 , further comprising:
identifying that the memory device has completed a current access operation, wherein locking the bank occurs after the current access operation is complete.

6. The method of claim 1 , further comprising:
receiving, from the host device, a message that includes information configured to unlock the bank to enable an additional operation to be performed on the bank based at least in part on transmitting the indication.

7. The method of claim 1 , further comprising:
determining that the command is a training command, wherein receiving the command occurs during initialization of the memory device.

8. The method of claim 1 , further comprising:
identifying a state of the bank associated with the memory cell based at least in part on receiving the command, wherein transmitting the indication to the host device is based at least in part on the state of the bank when the command is received.

9. The method of claim 1 , wherein the memory device comprises the bank having one or more rows of memory cells, wherein at least one of the one or more rows comprises the memory cell.

10. The method of claim 1 , wherein the command comprises a row activation command, and wherein determining that the timing threshold would be violated comprises:
determining that a row of the bank of the memory device is open, the bank is precharging and a row precharge time (tRP) has not elapsed, or a row refresh cycle time (tRFC) associated with a refresh command has not elapsed, or any combination thereof.

11. The method of claim 1 , wherein the command comprises a row precharge command, and wherein determining that the timing threshold would be violated comprises:
determining that no row of the bank of the memory device is open, a row of the bank is open and a row address strobe time (tRAS) has not elapsed, a write recovery time (tWR) associated with a write command has not elapsed, a read to precharge time (tRTP) associated with a read command has not elapsed, or any combination thereof.

12. The method of claim 1 , wherein the command comprises a write command, and wherein determining that the timing threshold would be violated comprises:
determining that the bank of the memory device is idle or precharging, a row of the bank is open and an activate to write delay time (tRCDWR) has not elapsed, a column to column delay time (tCCD) associated with a preceding write command has not elapsed, a read to write time (tRTW) associated with a preceding read command has not elapsed, or any combination thereof.

13. The method of claim 1 , wherein the command comprises a read command, and wherein determining that the timing threshold would be violated comprises:
determining that the bank of the memory device is idle or is precharging, the bank is open and an activate to read delay time (tRCDRD) has not elapsed, a column to column delay time (tCCD) associated with a preceding read command has not elapsed, a write to read time (tWTR) associated with a preceding write command has not elapsed, or any combination thereof.

14. The method of claim 1 , wherein the command comprises a refresh command, and wherein determining that the timing threshold would be violated comprises:
determining that a row of a bank of the memory device is open, the bank is precharging and a row precharge time (tRP) has not elapsed, or any combination thereof.

15. The method of claim 1 , further comprising:
refraining from executing the access operation based at least in part on determining that the timing threshold would be violated using the detection component, wherein transmitting the indication occurs after refraining from executing the access operation.

16. An apparatus, comprising:
an array of memory cells comprising one or more storage components;
a command decoder configured to receive, from a host device, a command to perform an access operation on a memory cell of the array of memory cells;
a detection component configured to determine a type of the command received by the command decoder, from a plurality of types of commands, based at least in part on receiving the command from the host device;
a detection component configured to determine whether a timing threshold associated with the memory cell would be violated by performing the access operation, wherein the timing threshold is based at least in part on the type of command received from the host device, and wherein a bank associated with the memory cell is configured to be locked to prevent additional operations from being performed on the bank based at least in part on the detection component determining that the timing threshold would be violated by performing the access operation; and
a transmitter configured to transmit an indication that performing the command would violate the timing threshold based at least in part on determining that the timing threshold would be violated using the detection component.

17. The apparatus of claim 16 , further comprising:
a selection component configured to select the timing threshold from a set of timing thresholds based at least in part on a type of the command received from the host device, wherein the detection component is configured determine whether the timing threshold would be violated is based at least in part on the selection component selecting the timing threshold.

18. The apparatus of claim 16 , wherein the detection compon

Assignees

• Micron Technology Inc

Inventors

• Richter Michael Dieter
• Balb Markus

Classifications

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C7/1063

  Control signal output circuits, e.g. status or busy flags, feedback command signals · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0673

  Single storage device · CPC title