Protocol checking logic circuit for memory system reliability

Patent metadata

Field	Value
Publication number	US-9317366-B2
Application number	US-201514593257-A
Country	US
Kind code	B2
Filing date	Jan 9, 2015
Priority date	Jun 21, 2012
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A buffer integrated circuit device. The device comprising an output driver formed on the substrate member, the output driver having at least a command bus and an address bus. The device has a protocol and parity checking block (“Block”). The device has a table configured in the block. The table is programmable with a plurality of timing parameters. The device has a memory state block coupled to the table and a command history table coupled to the table to process protocol information for all commands that pass through the Block. The buffer integrated circuit device utilizes the protocol checking functionality to prevent failure propagation and enables data protection even in the case of host memory controller failure or system-level failure of any signal or signals on the command, control and address bus from the host memory controller to the buffer integrated device.

First claim

The invention claimed is:

1. A computing system, the system comprising:
a buffer integrated circuit device comprising:
a substrate member comprising a silicon bearing material;
an output driver formed on the substrate member, the output driver having at least a command bus and an address bus, the command bus and the address bus being configured to a plurality of memory devices;
a protocol and parity checking block (“Block”), the protocol and parity checking block comprising a protocol circuit formed on the silicon bearing material and a parity circuit configured with the protocol circuit;
a table configured in the block, the table being programmable with a plurality of timing parameters, the plurality of timing parameters being at least one or two of tCL, tRCD, tRP, tWR, tAL, tRFC, tRRD, tCCD, tRAS, or tCWL;
a memory state block, the memory state block coupled to the table; and
a command history table, the command history table coupled to the table, and configured with the memory state block to process protocol information for all commands that pass through the Block; and
a host memory controller in communication with the buffer integrated circuit device.

2. The device of claim 1 wherein the Block blocks propagation of an erroneous command capable of causing any of the memory devices to an unknown or undefined state; and configured to transmit a predefined command sequence to set the memory devices to a safe or known state during a catastrophic failure of a host memory controller or any signal or signals on the command bus, the control bus, and address bus coupled to the host memory controller.

3. The device of claim 1 wherein the Block maintains that only a command that respect a timing and a sequence protocol of a defined memory access protocol is allowed to propagate through to the memory devices.

4. The device of claim 1 further comprising a channel for parity information.

5. The device of claim 1 Block is configured to process information in the command bus, the control bus and the address bus to identify an erroneous command or erroneous address bus information, or erroneous control timing, and configured to block the erroneous command, erroneous control or erroneous address bus information and preserve a known state of the plurality of memory devices; and configured to initiate a process to maintain the plurality of memory devices in the known state and preserve the integrity of data contained therein.

6. The device of claim 1 further comprising an address input receiver; and an address driver.

7. The device of claim 1 further comprising a multiplexer coupled to the host memory controller.

8. The device of claim 1 further comprising a PLL normally coupled to the host memory controller, but may be decoupled from the host memory controller upon the detection of failure by the protocol checking block.

9. The device of claim 1 further comprising a VerfCA reference voltage input circuit coupled to the host memory controller.

10. The device of claim 1 further comprising a System Management Bus (SMBus) port coupled to the host SMBus controller.

11. A computing system comprising:
a buffer integrated circuit device comprising:
a substrate member comprising a silicon bearing material;
an output driver formed on the substrate member, the output driver having at least a command bus and an address bus, the command bus and the address bus being configured to a plurality of memory devices;
a protocol and parity checking block (“Block”), the protocol and parity checking block comprising a protocol circuit formed on the silicon bearing material and a parity circuit configured with the protocol circuit, the Block is configured to process information in both the command bus and the address bus to identify an erroneous command or erroneous address bus information and configured to block the erroneous command or erroneous address bus information and preserve a known state of the plurality of memory devices; and configured to initiate a process to maintain the plurality of memory devices in the known state; and
a table configured in the block, the table being programmable with a plurality of timing parameters, the plurality of timing parameters being at least one or two of tCL, tRCD, tRP, tWR, tAL, tRFC, tRRD, tCCD, tRAS, tWTR, tRTP, tCKE, tFAW, or tCWL;
a memory state block, the memory state block coupled to the table; and
a command history table, the command history table coupled to the table, and configured with the memory state block to process protocol information for all commands that pass through the Block; and

a host memory controller coupled to the buffer integrated circuit device.

12. The device of claim 8 wherein the Block comprises a plurality of rank state protocol checkers, each of the rank state protocol checkers comprising a plurality of bank state protocol checkers.

13. The device of claim 8 wherein the Block is configured to process all single point failures and instruct the plurality of memory devices to a known or predefined state.

14. The device of claim 8 wherein the Block is characterized as a hierarchical configuration including state of a module, rank of a module, and bank within each rank.

15. The device of claim 8 wherein the Block is characterized as a hierarchical configuration including state of a module, rank of a module, and bank within each rank and is configured to protect against all single point failures associated with the DIMM or a host computer.

16. A method for operating a host computer system coupled to a DIMM apparatus, the DIMM apparatus comprising a plurality of memory devices, each of the plurality of memory devices being coupled to a separate buffer device coupled to a host computer, the separate buffer device comprising a substrate member comprising a silicon bearing material, an output driver formed on the substrate member, the output driver having at least a command bus and an address bus, the command bus and the address bus being configured to the plurality of memory devices, and a protocol and parity checking block (“Block”), the protocol and parity checking block comprising a protocol circuit formed on the silicon bearing material and a parity circuit configured with the protocol circuit, a table configured in the block, the table being programmable with a plurality of timing parameters, the plurality of timing parameters being at least one or two of tCL, tRCD, tRP, tWR, tAL, tRFC, tRRD, tCCD, tRAS, tWTR, tRTP, tCKE, tFAW, or tCWL; a memory state block, the memory state block coupled to the table; and a command history table, the command history table coupled to the table, the method comprising:
transferring information to and from the buffer device from the host computer system or the plurality of memory devices;
processing the information from either or both a command bus or/and an address bus to identify an erroneous command or erroneous address bus information;
blocking the erroneous command or erroneous address bus information; and
transferring instructions to preserve or return the plurality of memory devices to a known state; and
processing protocol information for all commands that pass through the Block.

17. The method of claim 16 wherein the Block comprises a plurality of rank state protocol checkers, each of the rank state protocol checkers comprising a plurality of bank state protocol checkers.

18. The method of claim 16 wherein the Block is configured to process all single point failures and instruct the plurality of memory devices to a known or predefined state.

Assignees

• Inphi Corp

Inventors

• Wang David

Classifications

• G06F11/1016 Primary

  Error in accessing a memory location, i.e. addressing error · CPC title

• G06F11/1004

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G06F11/1076 Primary

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• G06F11/008

  Reliability or availability analysis · CPC title

• G06F12/00

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title