Hardware command training for memory using write leveling mechanism

Patent metadata

Field	Value
Publication number	US-9607714-B2
Application number	US-201213728953-A
Country	US
Kind code	B2
Filing date	Dec 27, 2012
Priority date	Dec 26, 2012
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A method of training a command signal for a memory module. The method includes programming a memory controller into a mode where a single bit of an address signal is active for a single clock cycle. The method then programs a programmable delay line of the address signal with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode. A write leveling procedure is then performed and a response to the write leveling procedure is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.

First claim

What is claimed is:

1. A method of training a command signal for a memory module, said method comprising:
programming a memory controller into a mode wherein a first bit of an address signal is active for a single clock cycle;
programming a first programmable delay line of said address signal with a delay value, such that said address signal is delayed by said delay value;
initializing said memory module;
during said initialization, sending said first bit of said address signal delayed by said delay value as a write leveling mode register set command, wherein said first bit is set at a first level;
placing said memory module in a write leveling mode when said first bit is sampled at said first level at said memory module;
at said memory controller, performing a write leveling procedure and determining a response thereto from said memory module;
determining said memory module is in a pass state when said response comprises said first level and indicates said memory module is in said write leveling mode;
determining said memory module is in an error state when said response comprises a second level opposite said first level and indicates said memory module is not in said write leveling mode; and
programming a second programmable delay line of said command signal with said delay value when said memory module is in a pass state.

2. The method of claim 1 further comprising:
resetting said memory module upon a determination of said error state;
reprogramming said programmable delay line with another delay value; and
repeating said placing said memory module in said write leveling mode, said performing said write leveling procedure, and said determining said memory module is in said pass state or in said error state.

3. The method of claim 2 further comprising determining a range of delay values that result in said memory module determined to be in said pass state.

4. The method of claim 1 further comprising maintaining a frequency of said memory controller constant and maintaining a frequency of said address signal constant.

5. The method of claim 1 wherein a plurality of bits of said address signal except for said first bit are active for a programmable time period.

6. The method of claim 1 wherein said determining said memory module is in a pass state or an error state comprises:
determining that said memory module is in said pass state when a feedback from said memory module changes from a binary zero to a binary one; and
determining that said memory module is in said error state when said feedback remains a binary zero.

7. The method of claim 1 , wherein said command signal is taken from a group consisting of said address (A) signal, a bank address (BA) signal, a row address strobe (RAS#), a column access strobe (CAS#), a chip select (CS#), and a write enable (WE).

8. A non-transitory computer readable storage medium having stored thereon, computer executable instructions that, if executed by a computer system cause the computer system to perform a method of training a command signal for a memory module, said method comprising:
programming a memory controller into a mode wherein a first bit of said address signal is active for a single clock cycle;
programming a first programmable delay line of said address signal with a delay value, such that said address signal is delayed by said delay value;
initializing said memory module;
during said initialization, sending said first bit of said address signal delayed by said delay value as a write leveling mode register set command, wherein said first bit is set at a first level;
placing said memory module in a write leveling mode when said first bit is sampled at said first level at said memory module;
at said memory controller, performing a write leveling procedure and determining a response thereto from said memory module; and
determining said memory module is in a pass state when said response comprises said first level and indicates said memory module is in said write leveling mode;
determining said memory module is in an error state when said response comprises a second level opposite said first level and indicates said memory module is not in said write leveling mode; and
programming a second programmable delay line of said command signal with said delay value when said memory module is in a pass state.

9. The computer readable storage medium of claim 8 , wherein said method further comprises:
resetting said memory module upon a determination of said error state;
reprogramming said programmable delay line with another delay value; and
repeating said placing said memory module in said write leveling mode, said performing said write leveling procedure, and said determining said memory module is in said pass state or in said error state.

10. The computer readable storage medium of claim 9 wherein said method further comprises determining a range of delay values that result in said memory module determined to be in said pass state.

11. The computer readable storage medium of claim 8 wherein said method further comprises maintaining a frequency of said memory controller constant and maintaining a frequency of said address signal constant.

12. The computer readable storage medium of claim 8 wherein a plurality of bits except for said first bit of said address signal are active for a programmable time period.

13. The computer readable storage medium of claim 8 wherein said determining said memory module is in a pass state or an error state comprises:
determining that said memory module is in said pass state when a feedback from said memory module changes from a binary zero to a binary one; and
determining that said memory module is in said error state when said feedback remains a binary zero.

14. The computer readable storage medium of claim 8 , wherein said command signal is taken from a group consisting of said address (A) signal, a bank address (BA) signal, a row address strobe (RAS#), a column access strobe (CAS#), a chip select (CS#), and a write enable (WE).

15. A system comprising:
a processor coupled to a non-transitory computer readable storage media using a bus and executing computer readable code which causes the computer system to perform a method of training a command signal for a memory module, said method comprising:
programming a memory controller into a mode wherein a first bit of said address signal is active for a single clock cycle;
programming a first programmable delay line of said address signal with a delay value, such that said address signal is delayed by said delay value;
initializing said memory module;
during said initialization, sending said first bit of said address signal delayed by said delay value as a write leveling mode register set command, wherein said first bit is set at a first level;
placing said memory module in a write leveling mode when said first bit is sampled at said first level at said memory module;
at said memory controller, performing a write leveling procedure and determining a response thereto from said memory module; and
determining said memory module is in a pass state when said response comprises said first level and indicates said memory module is in said write leveling mode;
determining said memory module is in an error state when said response comprises a second level opposite said first level and indicates said memory module is not in said write leveling mode; and
programming a second programmable delay line of said command signal with said delay value when said memory module is in a pass state.

16. The system of claim 15 , wherein said me

Assignees

• Nvidia Corp

Inventors

• Malladi Venkata Ramana
• Cheng Tony Yuhsiang
• Raghava Sharath
• Kumar Ambuj
• Sahni Arunjit
• Lam Paul

Classifications

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C2207/2254

  Calibration · CPC title

• G11C7/20

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title

• G11C29/023 Primary

  in clock generator or timing circuitry · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title