Shift register unit, gate driving circuit, display device and driving method

Patent metadata

Field	Value
Publication number	US-10950320-B2
Application number	US-201916535412-A
Country	US
Kind code	B2
Filing date	Aug 8, 2019
Priority date	Sep 28, 2018
Publication date	Mar 16, 2021
Grant date	Mar 16, 2021

Abstract

A shift register unit including a first output circuit configured to transfer a clock signal at a clock signal terminal to a signal output terminal as an output signal in response to a first node being at an active potential, a second output circuit configured to transfer the clock signal at the clock signal terminal to a carry output terminal as a carry output signal in response to the first node being at the active potential, and a delay circuit configured to generate a delayed version of a carry input signal in response to the carry input signal at a carry input terminal being active, and to transfer an inactive voltage at a first voltage terminal to the signal output terminal in response to the delayed version of the carry input signal being active.

First claim

What is claimed is:

1. A shift register unit, comprising:
a signal input terminal configured to receive an input signal;
a reset input terminal configured to receive a reset signal;
a carry input terminal configured to receive a carry input signal;
a clock signal terminal configured to receive a clock signal;
a signal output terminal configured to output an output signal;
a carry output terminal configured to output a carry output signal;
a first voltage terminal configured to receive an inactive voltage;
a second voltage terminal configured to receive an inactive voltage;
a first output circuit configured to transfer the clock signal at the clock signal terminal to the signal output terminal as the output signal in response to a first node being at an active potential, wherein the first node is configured to be at the active potential in response to the input signal at the signal input terminal being active and to be at an inactive potential in response to the reset signal at the reset input terminal being active;
a second output circuit configured to transfer the clock signal at the clock signal terminal to the carry output terminal as the carry output signal in response to the first node being at the active potential; and
a delay circuit configured to generate a delayed version of the carry input signal in response to the carry input signal at the carry input terminal being active, and to transfer the inactive voltage at the first voltage terminal to the signal output terminal in response to the delayed version of the carry input signal being active.

2. The shift register unit of claim 1 , further comprising:
a first input circuit configured to transfer the input signal at the signal input terminal to the first node in response to the input signal being active; and
a second input circuit configured to transfer the inactive voltage at the second voltage terminal to the first node in response to the reset signal at the reset input terminal being active.

3. The shift register unit of claim 2 , wherein the first input circuit comprises:
a sixth transistor comprising a gate connected to the signal input terminal, a first electrode connected to the signal input terminal, and a second electrode connected to the first node.

4. The shift register unit of claim 2 , wherein the second input circuit comprises:
a seventh transistor comprising a gate connected to the reset input terminal, a first electrode connected to the first node, and a second electrode connected to the second voltage terminal.

5. The shift register unit of claim 1 , further comprising:
an initialization signal terminal configured to receive an initialization signal; and
an initialization circuit configured to transfer the inactive voltage at the second voltage terminal to the first node in response to the initialization signal at the initialization signal terminal being active.

6. The shift register unit of claim 5 , wherein the initialization circuit comprises:
an eighth transistor comprising a gate connected to the initialization signal terminal, a first electrode connected to the first node, and a second electrode connected to the second voltage terminal.

7. The shift register unit of claim 1 , further comprising:
a reset circuit configured to transfer the inactive voltage at the first voltage terminal to the signal output terminal in response to the reset signal at the reset input terminal being active.

8. The shift register unit of claim 7 , wherein the reset circuit comprises:
a ninth transistor comprising a gate connected to the reset input terminal, a first electrode connected to the signal output terminal, and a second electrode connected to the first voltage terminal.

9. The shift register unit of claim 1 , further comprising:
a third voltage terminal configured to receive a first voltage signal;
a first node control circuit configured to set a potential at a second node based upon a potential at the first node, the first voltage signal at the third voltage terminal, and the inactive voltage at the second voltage terminal;
a first voltage pull circuit configured to transfer the inactive voltage at the first voltage terminal to the signal output terminal in response to the potential at the second node being active; and
a second voltage pull circuit configured to transfer the inactive voltage at the second voltage terminal to the carry output terminal in response to the potential at the second node being active.

10. The shift register unit of claim 9 , further comprising:
a first noise reduction circuit configured to transfer the inactive voltage at the second voltage terminal to the first node in response to the potential at the second node being active.

11. The shift register unit of claim 9 , further comprising:
a fourth voltage terminal configured to receive a second voltage signal;
a second node control circuit configured to set a potential at a third node depending upon the potential at the first node, the second voltage signal at the fourth voltage terminal, and the inactive voltage at the second voltage terminal;
a third voltage pull circuit configured to transfer the inactive voltage at the first voltage terminal to the signal output terminal in response to the potential at the third node being active; and
a fourth voltage pull circuit configured to transfer the inactive voltage at the second voltage terminal to the carry output terminal in response to the potential at the third node being active.

12. The shift register unit of claim 11 , further comprising:
a second noise reduction circuit configured to transfer the inactive voltage at the second voltage terminal to the first node in response to the potential at the third node being active.

13. The shift register unit of claim 11 ,
wherein the second node control circuit comprises a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor,
wherein the seventeenth transistor comprises a gate connected to the fourth voltage terminal, a first electrode connected to the fourth voltage terminal, and a second electrode connected to a gate of the eighteenth transistor,
wherein the eighteenth transistor comprises a gate connected to the second electrode of the seventeenth transistor, a first electrode connected to the fourth voltage terminal, and a second electrode connected to the third node,
wherein the nineteenth transistor comprises a gate connected to the first node, a first electrode connected to the gate of the eighteenth transistor, and a second electrode connected to the second voltage terminal,
wherein the twentieth transistor comprises a gate connected to the first node, a first electrode connected to the third node, and a second electrode connected to the second voltage terminal,
wherein the third voltage pull circuit comprises a twenty-first transistor comprising a gate connected to the third node, a first electrode connected to the signal output terminal, and a second electrode connected to the first voltage terminal, and
wherein the fourth voltage pull circuit comprises a twenty-second transistor comprising a gate connected to the third node, a first electrode connected to the carry output terminal, and a second electrode connected to the second voltage terminal.

14. The shift register unit of claim 9 ,
wherein the first node control circuit comprises a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor,
wherein the tenth transistor comprises a gate connected to the third voltage terminal, a first electrode connected to the third voltage terminal, and a secon

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Xie Yongxian
• Wang Hui
• Zou Yifeng

Classifications

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2320/0252

  Improving the response speed · CPC title