Shift register and method for driving the same, gate driving circuit and display apparatus

Patent metadata

Field	Value
Publication number	US-11074844-B2
Application number	US-202016835698-A
Country	US
Kind code	B2
Filing date	Mar 31, 2020
Priority date	Jul 31, 2019
Publication date	Jul 27, 2021
Grant date	Jul 27, 2021

Abstract

The present disclosure provides a shift register and a method for driving the same, a gate driving circuit, and a display apparatus. The shift register includes: a node control sub-circuit configured to control a potential at a pull-up node under control of a signal input terminal and a reset terminal; an output sub-circuit configured to provide an output signal to a signal output terminal based on a signal at a clock signal terminal under control of the pull-up node; and at least one gating sub-circuit connected to at least one de-noising node respectively, and each configured to de-noise a respective de-noising node connected thereto independently of the potential at the pull-up node under control of a trigger signal terminal, wherein the at least one de-noising node includes at least one of the pull-up node and the signal output terminal.

First claim

We claim:

1. A shift register, comprising:
a node control sub-circuit connected to a signal input terminal, a reset terminal, and a pull-up node, and configured to control a potential at the pull-up node under control of the signal input terminal and the reset terminal;
an output sub-circuit connected to the pull-up node, a clock signal terminal, and a signal output terminal, and configured to provide an output signal to the signal output terminal based on a signal at the clock signal terminal under control of the pull-up node; and
at least one gating sub-circuit connected to at least one de-noising node respectively, each gating sub-circuit being configured to de-noise a respective de-noising node connected thereto independently of the potential at the pull-up node under control of a trigger signal terminal, wherein the at leas t one de-noising node comprises at least one of the pull-up node and the signal output terminal;
wherein each of the at least one gating sub-circuit comprises a switching sub-circuit and a de-noising sub-circuit, wherein:
the switching sub-circuit has a first terminal connected to the de-noising node, and a second terminal connected to the de-noising sub-circuit, and is configured to connect the first terminal to the second terminal or isolate the first terminal from the second terminal under control of the trigger signal terminal; and
the de-noising sub-circuit is connected to a pull-down node and the second terminal of the switching sub-circuit, and is configured to de-noise the second terminal of the switching sub-circuit under control of the pull-down node.

2. The shift register according to claim 1 , wherein the trigger signal terminal comprises a first trigger signal terminal and a second trigger signal terminal, and the switching sub-circuit comprises a first transistor, a second transistor, a third transistor, and a first capacitor, wherein:
the first transistor has a gate connected to a gating node, a first electrode acting as the first terminal of the switching sub-circuit, and a second electrode acting as the second terminal of the switching sub-circuit;
the second transistor has a gate connected to the first trigger signal terminal, a first electrode connected to a first voltage terminal, and a second electrode connected to the gating node;
the third transistor has a gate connected to the second trigger signal terminal, a first electrode connected to the gating node, and a second electrode connected to a second voltage terminal; and
the first capacitor has a first terminal connected to the gating node, and a second terminal connected to the second voltage terminal.

3. The shift register according to claim 2 , wherein the first trigger signal terminal is the reset terminal, and the second trigger signal terminal is connected to a signal input terminal of another shift register in a gate driving circuit where the shift register is located.

4. The shift register according to claim 1 , wherein the pull-down node comprises a first pull-down node and a second pull-down node, and the de-noising sub-circuit comprises a fourth transistor and a fifth transistor, wherein:
the fourth transistor has a gate connected to the first pull-down node, a first electrode connected to the second terminal of the switching sub-circuit, and a second electrode connected to a second voltage terminal; and
the fifth transistor has a gate connected to the second pull-down node, a first electrode connected to the second terminal of the switching sub-circuit, and a second electrode connected to the second voltage terminal.

5. The shift register according to claim 1 , wherein the node control sub-circuit comprises:
a pull-up node control sub-circuit connected to the signal input terminal, the reset terminal, and the pull-up node, and configured to input a signal at the signal input terminal to the pull-up node, and reset the potential at the pull-up node under control of a signal at the reset terminal; and
a pull-down node control sub-circuit connected to a first control terminal, a second control terminal, a first pull-down node and a second pull-down node, and configured to control a potential at the first pull-down node under control of a signal at the first control terminal and control a potential at the second pull-down node under control of a signal at the second control terminal.

6. The shift register according to claim 5 , wherein the pull-up node control sub-circuit comprises a sixth transistor and a seventh transistor, wherein:
the sixth transistor has a gate and a first electrode connected to the signal input terminal, and a second electrode connected to the pull-up node; and
the seventh transistor has a gate connected to the reset terminal, a first electrode connected to the pull-up node, and a second electrode connected to a second voltage terminal.

7. The shift register according to claim 5 , wherein the pull-down node control sub-circuit comprises an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor, wherein:
the eighth transistor has a gate and a first electrode connected to the first control terminal, and a second electrode connected to a gate of the ninth transistor;
the ninth transistor has the gate connected to the second electrode of the eighth transistor, a first electrode connected to the first control terminal, and a second electrode connected to the first pull-down node;
the tenth transistor has a gate and a first electrode connected to the second control terminal, and a second electrode connected to a gate of the eleventh transistor; and
the eleventh transistor has the gate connected to the second electrode of the tenth transistor, a first electrode connected to the second control terminal, and a second electrode connected to the second pull-down node.

8. The shift register according to claim 1 , wherein the signal output terminal comprises a first signal output terminal and a second signal output terminal, and the output sub-circuit comprises a second capacitor, a twelfth transistor, and a thirteenth transistor, wherein:
the twelfth transistor has a gate connected to the pull-up node, a first electrode connected to the clock signal terminal, and a second electrode connected to the first signal output terminal;
the thirteenth transistor has a gate connected to the pull-up node, a first electrode connected to the clock signal terminal, and a second electrode connected to the second signal output terminal; and
the second capacitor has a first terminal connected to the pull-up node, and a second terminal connected to the first signal output terminal.

9. The shift register according to claim 1 , wherein the at least one de-noising node comprises the pull-up node, and the at least one gating sub-circuit comprises a first gating sub-circuit connected to the pull-up node.

10. The shift register according to claim 1 , wherein the signal output terminal comprises a first signal output terminal, the at least one de-noising node comprises the pull-up node and the first signal output terminal, and the at least one gating sub-circuit comprises a first gating sub-circuit connected to the pull-up node and a second gating sub-circuit connected to the first signal output terminal.

11. The shift register according to claim 1 , wherein the signal output terminal comprises a first signal output terminal and a second signal output terminal, the at least one de-noising node comprises the pull-up node, the first signal output terminal and the second signal output terminal, and the at least one gating sub-circuit comprises a first gating sub-circuit connected to the pull-up node, a second gating sub-circuit connected to the first signa

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Zou Yifeng
• Zheng Mindong
• Deng Chuanfeng

Classifications

• G09G2320/02

  Improving the quality of display appearance · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3208 Primary

  organic, e.g. using organic light-emitting diodes [OLED] · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title