Shift register, driving method thereof and gate driving device

Patent metadata

Field	Value
Publication number	US-2018190232-A1
Application number	US-201715680441-A
Country	US
Kind code	A1
Filing date	Aug 18, 2017
Priority date	Jan 3, 2017
Publication date	Jul 5, 2018
Grant date	—

Abstract

A shift register includes an input circuit, a first reset circuit, an output circuit, a second reset circuit and a first pull-down control circuit. The input circuit may control a voltage of the first node according to a reset signal from a reset signal terminal. The first reset circuit may reset the voltage of the first node according to the reset signal from the reset signal terminal. The output circuit may control an output signal of a signal output terminal according to the voltage of the first node. The second reset circuit may reset the voltage of the first node and the output signal according to a voltage of a second node. The first pull-down control circuit may control the voltage of the second node according to the voltage of the first node based on a first auxiliary voltage signal and a second auxiliary voltage signal, wherein a phase of the first auxiliary voltage signal is opposite to a phase of the second auxiliary voltage signal, and each duty cycles is 50%.

First claim

I/We claim:

1 . A shift register, comprising:
an input circuit, coupled to a signal input terminal, a first voltage signal terminal and a first node, and configured to supply a first voltage signal from the first voltage signal terminal to the first node according to an input signal from the signal input terminal; a first reset circuit, coupled to a reset signal terminal, a second voltage signal terminal and the first node, and configured to supply a first reset signal from the second voltage signal terminal to the first node according to a second reset signal from the reset signal terminal, so as to reset a voltage of the first node; an output circuit, coupled to a clock signal terminal, a signal output terminal and the first node, and configured to supply a clock signal from the clock signal terminal to the signal output terminal as an output signal, according to the voltage of the first node; a second reset circuit, coupled to a third voltage signal terminal, the first node, a second node and the signal output terminal, and configured to supply a third voltage signal from the third voltage signal terminal to the first node and the signal output terminal according to a voltage of the second node, so as to reset the voltage of the first node and the output signal; and a first pull-down control circuit, coupled to the first node, the second node, the third voltage signal terminal, a first auxiliary voltage signal terminal and a second auxiliary voltage signal terminal, and configured to control the voltage of the second node according to the voltage of the first node; wherein a phase of a first auxiliary voltage signal from the first auxiliary voltage signal terminal is opposite to that of a second auxiliary voltage signal from the second auxiliary voltage signal terminal, each with a duty ratio of 50%.

2 . The shift register according to claim 1 , wherein the input circuit comprises:
a first transistor having a control electrode coupled to the signal input terminal, a first electrode coupled to the first voltage signal terminal, and a second electrode coupled to the first node.

3 . The shift register according to claim 2 , wherein the first reset circuit comprises:
A second transistor having a control electrode coupled to the reset signal terminal, a first electrode coupled to the second voltage signal terminal, and a second electrode coupled to the first node.

4 . The shift register according to claim 3 , wherein the output circuit comprises:
a third transistor having a control electrode coupled to the first node, a first electrode coupled to the clock signal terminal, and a second electrode coupled to the signal output terminal; and a first capacitor coupled between the first node and the signal output terminal.

5 . The shift register according to claim 4 , wherein the second reset circuit comprises:
a fourth transistor having a control electrode coupled to the second node, a first electrode coupled to the third voltage signal terminal, and a second electrode coupled to the first node; and a fifth transistor having a control electrode coupled to the second node, a first electrode coupled to the third voltage signal terminal, and a second electrode coupled to the signal output terminal.

6 . The shift register of claim 5 , wherein the first pull-down control circuit comprises:
a sixth transistor having a control electrode coupled to the first node, a first electrode coupled to the third voltage signal terminal, and a second electrode coupled to the second node; a seventh transistor having a control electrode and a first electrode both coupled to the second auxiliary voltage signal terminal, and a second electrode coupled to the second node; and an eighth transistor having a control electrode and a first electrode both coupled to the first auxiliary voltage signal terminal, and a second electrode coupled to the second node.

7 . The shift register according to claim 6 , wherein
a width-to-length ratio of the seventh transistor is identical to a width-to-length ratio of the eighth transistor; and a width-to-length ratio of the sixth transistor is an integral multiple of the width-to-length ratios of the seventh transistor and the eighth transistor.

8 . The shift register according to claim 7 , wherein the first pull-down control circuit further comprises:
a ninth transistor having a control electrode coupled to the first node, a first electrode coupled to the third voltage signal terminal, and a second electrode coupled to the second node; wherein a width-to-length ratio of the ninth transistor is identical with the width-to-length ratio of the sixth transistor.

9 . The shift register according to claim 8 , further comprising:
a second pull-down control circuit, coupled to the second node and a start signal terminal, and configured to control a voltage of the second node according to a start signal from the start signal terminal.

10 . The shift register according to claim 9 , wherein the second pull-down control circuit comprises:
a tenth transistor having a control electrode and a first electrode both coupled to the start signal terminal, and a second electrode coupled to the second node.

11 . A method of driving the shift register according to claim 1 , comprising:
in a first time period, supplying, by the signal input terminal, the input signal to the input circuit so as to turn the input circuit on; outputting, by the first voltage signal terminal, the first voltage signal to the first node through the input circuit so as to turn the output circuit on; outputting, by the clock signal terminal, the clock signal to the signal output terminal through the output circuit; and controlling, by the first pull-down control circuit, the voltage of the second node according to the second auxiliary voltage signal supplied by the second auxiliary signal terminal and the third voltage signal supplied by the third voltage signal terminal; in a second time period, keeping the output circuit turned on to output the clock signal to the signal output terminal; and controlling the voltage of the second node by the first pull-down control circuit according to the first auxiliary voltage signal supplied by the first auxiliary voltage signal terminal and the third voltage signal; in a third time period, supplying, by the reset signal terminal, the reset signal to the first reset circuit so as to turn the first reset circuit on, and resetting the voltage of the first node to turn the output circuit off; and supplying the second auxiliary voltage signal to the second node so as to turn the second reset circuit on to reset the voltages of the first node and the signal output terminal; in a fourth time period, supplying the first auxiliary voltage signal to the second node to keep the second reset circuit turned on; and in a fifth time period, supplying the second auxiliary voltage signal to the second node to keep the second reset circuit turned on.

12 . The method according to claim 11 , wherein
the first voltage signal is at a high level, the second voltage signal is at a low level, the input signal is active during the first time period, and the reset signal is active during the third time period; or the first voltage signal is at a low level, the second voltage signal is at a high level, the input signal is active during the third time period, and the reset signal is active during the first time period.

13 . A method of driving the shift register according to claim 9 , comprising:
in a first time period, supplying, by the signal input terminal, the input signal to the input circuit so as to turn the input circuit

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Xue Wei
• Li Hongmin
• Song Ping
• Dong Zhifu

Classifications

• G09G3/3677 Primary

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• G09G2300/0426

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• G09G2300/0408

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• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title