Delay-based spread spectrum clock generator circuit

Patent metadata

Field	Value
Publication number	US-11323131-B2
Application number	US-202017089090-A
Country	US
Kind code	B2
Filing date	Nov 4, 2020
Priority date	Nov 6, 2019
Publication date	May 3, 2022
Grant date	May 3, 2022

Abstract

A delay chain circuit with series coupled delay elements receives a reference clock signal and outputs phase-shifted clock signals. A multiplexer circuit receives the phase-shifted clock signals and selects among the phase-shifted clock signals for output as in response to a selection signal. The selection signal is generated by a control circuit from a periodic signal having a triangular wave profile. A sigma-delta modulator converts the periodic signal to a digital signal, and an integrator circuit integrates the digital signal to output the selection signal. The selected phase-shifted clock signal is applied as the reference signal to a phase locked loop which generates a spread spectrum clock signal.

First claim

The invention claimed is:

1. A circuit, comprising:
a delay chain circuit having an input configured to receive a reference clock signal, the delay chain circuit including a plurality of delay elements coupled in series, wherein the delay chain circuit outputs a plurality of phase-shifted clock signals;
a first multiplexer circuit having inputs coupled to receive the plurality of phase-shifted clock signals and having a first selection input configured to receive a first selection signal which selects one of the plurality of phase-shifted clock signals for output; and
a control circuit configured to generate values for the first selection signal from a waveform signal having a periodic triangular wave profile, wherein the control circuit includes:
a sigma-delta modulator configured to convert the waveform signal to generate a modulated digital signal from which the values for the first selection signal are generated; and
a register circuit configured to latch the first selection signal in response to a control clock, wherein the control clock is a delayed version of the phase-shifted clock signal selected by the first selection signal and output by the first multiplexer circuit.

2. The circuit of claim 1 , further comprising a phase generator circuit configured to process the modulated digital signal and output the values of the first selection signal.

3. The circuit of claim 2 , wherein the phase generator circuit comprises a digital integrator circuit.

4. The circuit of claim 1 , further comprising a phase lock loop (PLL) circuit configured to receive the selected phase-shifted clock signal as a reference for generating a spread spectrum clock signal.

5. The circuit of claim 4 , wherein the sigma-delta modulator implements noise shaping to push quantization noise into a higher frequency domain and the PLL circuit has a low-pass response for filtering out the quantization noise.

6. The circuit of claim 1 , further comprising:
a compensation circuit configured to determine a number of delay elements within the delay chain circuit which change state in response to one cycle of the reference clock signal; and
wherein the control circuit adjusts a modulation depth of the waveform signal having the triangular wave profile in response to the determined number of delay elements.

7. The circuit of claim 1 , further comprising:
a compensation circuit configured to determine a number of delay elements within the delay chain circuit which change state in response to one cycle of the reference clock signal; and
wherein the control circuit adjusts a number of quantization levels for the sigma-delta modulator in response to the determined number of delay elements.

8. The circuit of claim 1 , wherein the control circuit further includes a digital waveform generator configured to generate the waveform signal having the triangular wave profile in response to the reference clock signal.

9. The circuit of claim 8 , wherein the triangular wave profile is defined by a modulation frequency and a modulation depth.

10. The circuit of claim 9 , wherein the modulation depth is scaled by a compensation value to account for process and voltage variation of the plurality of delay elements.

11. The circuit of claim 10 , wherein the compensation value is generated dependent on a number of delay elements within the delay chain circuit which change state in response to one cycle of the reference clock signal.

12. A circuit, comprising:
a delay chain circuit having an input configured to receive a reference clock signal, the delay chain circuit including a plurality of delay elements coupled in series, wherein the delay chain circuit outputs a plurality of phase-shifted clock signals;
a first multiplexer circuit having inputs coupled to receive the plurality of phase-shifted clock signals and having a first selection input configured to receive a first selection signal which selects one of the plurality of phase-shifted clock signals for output
a control circuit configured to generate values for the first selection signal from a waveform signal having a periodic triangular wave profile, wherein the control circuit includes:
a sigma-delta modulator configured to convert the waveform signal to generate a modulated digital signal from which the values for the first selection signal are generated; and

a register circuit configured to latch the first selection signal in response to a control clock, wherein the control clock is a further selected one of the plurality of phase-shifted clock signals.

13. The circuit of claim 12 , further comprising a second multiplexer circuit having inputs coupled to receive the plurality of phase-shifted clock signals and having a second selection input configured to receive a second selection signal which selects said further selected one of the plurality of phase-shifted clock signals for output by the second multiplexer circuit.

14. The circuit of claim 12 , wherein the second selection signal is a delayed version of the first selection signal generated by the control circuit.

15. The circuit of claim 12 , further comprising a phase generator circuit configured to process the modulated digital signal and output the values of the first selection signal.

16. The circuit of claim 15 , wherein the phase generator circuit comprises a digital integrator circuit.

17. The circuit of claim 12 , further comprising a phase lock loop (PLL) circuit configured to receive the selected phase-shifted clock signal as a reference for generating a spread spectrum clock signal.

18. The circuit of claim 12 , wherein the sigma-delta modulator implements noise shaping to push quantization noise into a higher frequency domain and the PLL circuit has a low-pass response for filtering out the quantization noise.

19. The circuit of claim 12 , further comprising:
a compensation circuit configured to determine a number of delay elements within the delay chain circuit which change state in response to one cycle of the reference clock signal; and
wherein the control circuit adjusts a modulation depth of the waveform signal having the triangular wave profile in response to the determined number of delay elements.

20. The circuit of claim 12 , further comprising:
a compensation circuit configured to determine a number of delay elements within the delay chain circuit which change state in response to one cycle of the reference clock signal; and
wherein the control circuit adjusts a number of quantization levels for the sigma-delta modulator in response to the determined number of delay elements.

21. The circuit of claim 13 , wherein the control circuit further includes a digital waveform generator configured to generate the waveform signal having the triangular wave profile in response to the reference clock signal.

22. The circuit of claim 21 , wherein the triangular wave profile is defined by a modulation frequency and a modulation depth.

23. The circuit of claim 22 , wherein the modulation depth is scaled by a compensation value to account for process and voltage variation of the plurality of delay elements.

24. The circuit of claim 23 , wherein the compensation value is generated dependent on a number of delay elements within the delay chain circuit which change state in response to one cycle of the reference clock signal.

25. A method, comprising:
selecting one of a plurality of phase-shifted clock signals for output in response

Assignees

• St Microelectronics Int Nv

Inventors

• Midha Gagan
• Chatterjee Kallol

Classifications

• H03M7/3022

  having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type · CPC title

• H03K7/08 Primary

  Duration or width modulation {; Duty cycle modulation} · CPC title

• H03M3/37

  Compensation or reduction of delay or phase error · CPC title

• H03M3/35 Primary

  using redundancy · CPC title

• H03M3/346

  by suppressing active signals at predetermined times, e.g. muting, using non-overlapping clock phases · CPC title