Spread spectrum clock generator

Patent metadata

Field	Value
Publication number	US-10348314-B2
Application number	US-201815888153-A
Country	US
Kind code	B2
Filing date	Feb 5, 2018
Priority date	Aug 30, 2016
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

A phase or frequency locked-loop circuit includes an oscillator configured to generate an output clock signal having a frequency set by an oscillator control signal. A modulator circuit receives a first signal and a second signal and is configured to generate a control signal having a value modulated in response to the first and second signals. A filter circuit generates the oscillator control signal by filtering the control signal. A delta-sigma modulator circuit operates to modulate the second signal in response to a modulation profile. As a result, the output clock signal is a spread spectrum clock signal.

First claim

What is claimed is:

1. A method for generating a spread spectrum clock signal, comprising:
generating a control signal having a value modulated in response to a first signal and a second signal;
filtering the control signal to generate an oscillator control signal;
generating an output clock signal having a frequency set by said oscillator control signal;
modulating the second signal in response to a modulation profile signal having an amplitude and frequency which produce a spread spectrum frequency characteristic for the output clock signal.

2. The method of claim 1 , wherein modulating comprises delta-sigma modulating.

3. The method of claim 1 , wherein the first signal is lock control signal generated in response to a phase comparison.

4. The method of claim 3 , further comprise phase locking a signal derived from the output clock signal to a reference frequency signal in order to generate the lock control signal.

5. The method of claim 4 , further comprising filtering the lock control signal to generate said first signal.

6. The method of claim 1 , wherein the first signal is a lock control signal generated in response to a count comparison.

7. The method of claim 6 , further comprise count locking a signal derived from the output clock signal to a reference count signal in order to generate the lock control signal.

8. The method of claim 7 , further comprising filtering the lock control signal to generate said first signal.

9. The method of claim 1 , wherein modulating the second signal in response to the modulation profile signal further comprises modulating the second signal in response to a combination of the modulation profile signal and a feedback modulation signal.

10. The method of claim 9 , further comprising frequency dividing the output clock signal to generate the feedback modulation signal.

11. The method of claim 1 , wherein modulating the second signal in response to the modulation profile signal further comprises modulating the second signal in response to a combination of the modulation profile signal and a reference frequency signal.

12. The method of claim 11 , further comprising phase locking a signal derived from the output clock signal to the reference frequency signal in order to generate a lock control signal.

13. The method of claim 12 , further comprising filtering the lock control signal to generate said first signal.

14. The method of claim 12 , further comprising frequency dividing the output clock signal to generate said signal derived from the output clock signal.

15. The method of claim 11 , further comprising count locking a signal derived from the output clock signal to a count reference signal in order to generate a lock control signal.

16. The method of claim 15 , further comprising filtering the lock control signal to generate said first signal.

17. The method of claim 15 , further comprising counting cycles of the output clock signal in comparison to said reference frequency signal to generate said signal derived from the output clock signal.

18. A method for generating a spread spectrum clock signal, comprising:
operating a phase-lock-loop to receive a reference frequency signal and generate an output clock signal having a frequency controlled by an oscillator control signal and phase locked to said reference frequency signal; and
applying a modulation to said oscillator control signal in response to a modulation profile signal having an amplitude and frequency which produce a spread spectrum frequency characteristic for the output clock signal.

19. The method of claim 18 , further comprising phase locking a signal derived from the output clock signal to the reference frequency signal.

20. The method of claim 18 , wherein applying the modulation to said oscillator control signal in response to the modulation profile signal further comprises modulating said oscillator control signal in response to a combination of the modulation profile signal and a feedback modulation signal.

21. The method of claim 20 , further comprising frequency dividing the output clock signal to generate the feedback modulation signal.

22. The method of claim 18 , wherein applying the modulation to said oscillator control signal in response to the modulation profile signal further comprises modulating said oscillator control signal in response to a combination of the modulation profile signal and a reference frequency signal.

23. The method of claim 22 , wherein operating the phase-lock-loop comprises phase locking a signal derived from the output clock signal to the reference frequency signal.

24. The method of claim 23 , further comprising frequency dividing the output clock signal to generate said signal derived from the output clock signal.

25. A method for generating a spread spectrum clock signal, comprising:
operating a count-lock-loop to receive a reference count signal and generate an output clock signal having a frequency controlled by an oscillator control signal and count locked to said reference count signal; and
applying a modulation to said oscillator control signal in response to a modulation profile signal so that said output clock signal has a spread spectrum characteristic.

26. The method of claim 25 , further comprising count locking a signal derived from the output clock signal to the reference count signal.

27. The method of claim 25 , wherein applying the modulation to said oscillator control signal in response to the modulation profile signal further comprises modulating said oscillator control signal in response to a combination of the modulation profile signal and a feedback modulation signal.

28. The method of claim 27 , further comprising frequency dividing the output clock signal to generate the feedback modulation signal.

29. The method of claim 25 , wherein applying the modulation to said oscillator control signal in response to the modulation profile signal further comprises modulating said oscillator control signal in response to a combination of the modulation profile signal and a reference frequency signal.

30. The method of claim 29 , wherein operating the count-lock-loop comprises count locking a signal derived from the output clock signal to a count reference signal.

31. The method of claim 30 , further comprising counting cycles of the output clock signal in comparison to said reference frequency signal to generate said signal derived from the output clock signal.

32. The method of claim 1 , wherein the modulation profile signal is a periodic wave.

33. The method of claim 32 , wherein the periodic wave is a triangular wave.

34. The method of claim 18 , wherein the modulation profile signal is a periodic wave.

35. The method of claim 34 , wherein the periodic wave is a triangular wave.

Assignees

• St Microelectronics Int Nv

Inventors

• Kumar Anand
• Midha Gagan

Classifications

• H03L7/1976

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• H03L7/093 Primary

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/0891

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title

• H03C3/095

  applying frequency modulation to the loop in front of the voltage controlled oscillator · CPC title