Method for fabricating semiconductor package

Patent metadata

Field	Value
Publication number	US-11322368-B2
Application number	US-202017037003-A
Country	US
Kind code	B2
Filing date	Sep 29, 2020
Priority date	Feb 14, 2020
Publication date	May 3, 2022
Grant date	May 3, 2022

Abstract

A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.

First claim

What is claimed is:

1. A method for fabricating a semiconductor package, the method comprising:
forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness;
forming a barrier layer on the release layer;
forming a redistribution layer on the barrier layer, wherein the redistribution layer includes a plurality of wirings and an insulating layer surrounding the plurality of wirings;
mounting a semiconductor chip on the redistribution layer to be electrically connected to the redistribution layer;
forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip;
attaching a second carrier substrate onto the molding layer;
removing the first carrier substrate and the release layer;
removing the barrier layer; and
attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.

2. The method for fabricating the semiconductor package of claim 1 , wherein the barrier layer includes a metal material.

3. The method for fabricating the semiconductor package of claim 2 , wherein the metal material includes copper (Cu).

4. The method for fabricating the semiconductor package of claim 1 , wherein the barrier layer includes the same material as the plurality of wirings.

5. The method for fabricating the semiconductor package of claim 1 , wherein the formation of the release layer includes
forming a first release layer having the first thickness on the first carrier substrate, and
forming a second release layer on the first release layer, wherein the second release layer has a third thickness and includes an opening exposing at least a part of the first release layer,
wherein the opening overlaps the first portion.

6. The method for fabricating the semiconductor package of claim 5 , wherein the third thickness ranges between about 3 μm and about 8 μm.

7. The method for fabricating the semiconductor package of claim 1 , wherein the removal of the release layer includes using a laser.

8. The method for fabricating the semiconductor package of claim 7 , wherein the laser does not pass into the redistribution layer because of the barrier layer.

9. The method for fabricating the semiconductor package of claim 1 , wherein the removal of the barrier layer and the second portion of the release layer exposes at least a part of the plurality of wirings of the redistribution layer, and
the solder ball is electrically connected to the exposed plurality of wirings.

10. The method for fabricating the semiconductor package of claim 1 , wherein the release layer includes the same material as the insulating layer.

11. The method for fabricating the semiconductor package of claim 1 , wherein the release layer includes a photosensitive insulating material.

12. A method for fabricating a semiconductor package, the method comprising:
forming a first release layer on a first carrier substrate;
forming a second release layer on the first release layer, wherein the second release layer includes an opening for exposing at least a part of the first release layer;
forming a barrier layer on the second release layer;
forming a redistribution layer on the barrier layer, wherein the redistribution layer includes a plurality of wirings and an insulating layer surrounding the plurality of wirings;
mounting a first semiconductor chip on the redistribution layer, wherein the first semiconductor chip is electrically connected to the redistribution layer;
attaching a second carrier substrate onto the first semiconductor chip;
removing the first carrier substrate, the first release layer and the second release layer using a laser;
removing the barrier layer; and
attaching a solder ball to a position of the redistribution layer from which the second release layer is removed,
wherein the first release layer and the second release layer include a photosensitive insulating material.

13. The method for fabricating the semiconductor package of claim 12 , wherein the first carrier substrate is a glass substrate.

14. The method for fabricating the semiconductor package of claim 12 , wherein the second release layer has a thickness ranging between about 3 μm and about 8 μm.

15. The method for fabricating the semiconductor package of claim 12 , wherein the barrier layer includes a metal material.

16. The method for fabricating the semiconductor package of claim 12 , further comprising:
after mounting the first semiconductor chip on the redistribution layer,
forming a first molding layer on the redistribution layer, wherein the first molding layer at least partially surrounds the first semiconductor chip and includes a penetration via penetrating the first molding layer; and
mounting a second semiconductor chip on the first molding layer,
wherein the second carrier substrate is attached onto the second semiconductor chip.

17. The method for fabricating the semiconductor package of claim 16 , wherein the second semiconductor chip is electrically connected to the redistribution layer through the penetration via.

18. The method for fabricating the semiconductor package of claim 12 , further comprising:
after mounting the first semiconductor chip on the redistribution layer,
forming a first molding layer on the redistribution layer, wherein the first molding layer at least partially surrounds the first semiconductor chip;
forming connection substrates at opposing sides of the first semiconductor chip, wherein the connection substrates include a plurality of sub-wiring and a base layer at least partially surrounding the plurality of sub-wiring; and
mounting a package on the first molding layer, wherein the package includes a substrate, a second semiconductor chip mounted on the substrate, and a second molding layer at least partially surrounding the second semiconductor chip on the substrate,
wherein the second carrier substrate is attached onto the second molding layer,
and
the second semiconductor chip is electrically connected to the redistribution layer through the substrate and the connection substrate.

19. A method for fabricating a semiconductor package, the method comprising:
forming a first release layer on a first carrier substrate;
forming a second release layer on the first release layer, wherein the second release layer includes a first opening for exposing at least a part of an upper surface of the first release layer;
forming a barrier layer on the second release layer, wherein the barrier layer extends along an upper surface of the second release layer and includes a metal material;
forming an electrode pad support layer on the barrier layer, wherein the electrode pad support layer exposes at least a part of the barrier layer and includes a second opening not overlapping the first opening;
forming a redistribution layer on the electrode pad support layer, wherein the redistribution layer includes a plurality of wirings and an insulating layer surrounding the plurality of wirings;
mounting a semiconductor chip on the redistribution layer;
forming a molding layer surrounding the semiconductor chip on the redistribution layer;
attaching a second carrier substrate onto the molding layer;
removing the first carrier substrate, the first release layer and the second release layer, using a laser;
removing the barrier layer;
form

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jung-Ho
• Park Jin-Woo
• Lee Seok Hyun
• Jang Jae Gwon
• Jeon Gwang Jae

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title