Memory module for platform with non-volatile storage

Patent metadata

Field	Value
Publication number	US-11322203-B2
Application number	US-202017066283-A
Country	US
Kind code	B2
Filing date	Oct 8, 2020
Priority date	Dec 9, 2016
Publication date	May 3, 2022
Grant date	May 3, 2022

Abstract

A system that includes a non-volatile memory subsystem having non-volatile memory. The system also includes a plurality of memory modules that are separate from the non-volatile memory subsystem. Each memory module can include a plurality of random access memory packages where each first random access memory package includes a primary data port and a backup data port. Each memory module can include a storage interface circuit coupled to the backup data ports of the random access memory packages. The storage interface circuit offloads data from the memory module in the event of a power loss by receiving data from the backup data ports of the random access memory packages and transmitting the data to the non-volatile memory subsystem.

First claim

What is claimed is:

1. A memory module comprising:
a plurality of random access memory devices configured to store data, each of the plurality of random access memory devices including a primary data port for transferring the data with a memory controller, and a backup data port for transferring the data with a non-volatile memory (NVM) data backup subsystem that is separate from the memory module;
wherein the memory module is configured to forward to the NVM data backup subsystem a signal received from the memory controller to backup the data stored in the plurality of random access memory devices, and receive a backup command from the NVM data backup subsystem responsive to forwarding the signal, and
wherein the memory module is configured to reconfigure primary data ports and backup data ports of the plurality of random access memory packages responsive to receiving the backup command from the NVM data backup subsystem such that the data is offloaded from the memory module to the NVM data backup subsystem via the backup data ports.

2. The memory module of claim 1 , wherein the memory module reconfigures the primary data ports and the backup data ports by disabling the primary data ports and enabling the backup data ports.

3. The memory module of claim 1 , wherein the signal is received from the memory controller due to an event of a power loss.

4. The memory module of claim 1 , further comprising:
a storage interface circuit coupled to the backup data ports of the plurality of random access memory devices, the storage interface circuit to offload the data by receiving the data from the backup data ports and offloading the data to the NVM data backup subsystem.

5. The memory module of claim 4 , wherein the storage interface circuit is configured to restore the data backed up to the NVM data backup subsystem to the memory module by receiving the data from the NVM data backup subsystem and writing the data to the backup data ports of the plurality of random access memory devices.

6. The memory module of claim 4 , further comprising:
a data backup connector;
wherein the storage interface circuit offloads the data to the NVM data backup subsystem via the data backup connector.

7. The memory module of claim 6 , wherein the data backup connector is configured to receive the signal from the memory controller and forward the signal to the NVM data backup subsystem.

8. The memory module of claim 5 , wherein the data backup connector comprises a ribbon cable connector or a dual in line memory module edge connector.

9. The memory module of claim 4 , further comprising:
an edge connector at an edge of the memory module; and
a plurality of data buffer circuits to buffer the data between the edge connector and the primary data ports of the plurality of random access memory devices,
wherein the plurality of data buffer circuits are disabled while the storage interface circuit is offloading the data.

10. The memory module of claim 4 , wherein a clock synchronization circuit in the plurality of random access memory devices is disabled while the storage interface circuit is offloading the data.

11. The memory module of claim 4 , wherein the storage interface circuit comprises a serializer circuit to serialize the data received from the backup data ports of the plurality of random access memory devices into serialized data, wherein the data offloaded to the NVM data backup subsystem is the serialized data.

12. The memory module of claim 11 , wherein each of the plurality of random access memory devices further comprises:
a random access memory core; and
multiplexing circuitry that is coupled to the random access memory core through a data access path, the multiplexing circuitry selectively coupling one of the primary data port and the backup data port of the random access memory device to the data access path at a time.

13. A method of operation of a memory module that includes a plurality of random access memory devices configured to store data, each of the plurality of random access memory devices including a primary data port for transferring the data with a memory controller, and a backup data port for transferring the data with a non-volatile memory (NVM) data backup subsystem that is separate from the memory module, the method comprising:
forwarding to the NVM data backup subsystem a signal received from the memory controller to backup the data stored in the plurality of random access memory devices;
receiving a backup command from the NVM data backup subsystem responsive to forwarding the signal; and
reconfiguring primary data ports and backup data ports of the plurality of random access memory devices responsive to receiving the backup command from the NVM data backup subsystem such that the data is offloaded from the memory module to the NVM data backup subsystem via the backup data ports.

14. The method of claim 13 , wherein reconfiguring the primary data ports and the backup data ports comprises disabling the primary data ports and enabling the backup data ports.

15. The method of claim 13 , wherein the signal is received from the memory controller due to an event of a power loss.

16. The method of claim 13 , further comprising:
restoring the data backed up to the NVM data backup subsystem to the memory module by receiving the data from the NVM data backup subsystem and writing the data to the backup data ports of the plurality of random access memory devices.

17. The method of claim 13 , wherein the data is offloaded to the NVM data backup subsystem via a data backup connector.

18. The method of claim 17 , wherein the signal is received from the memory controller at the data backup connector.

19. The method of claim 13 , further comprising:
disabling a plurality of data buffer circuits are while the data is offloaded to the NVM data backup subsystem, the plurality of data buffer circuits configured to buffer the data between an edge connector of the memory module and the primary data ports of the plurality of random access memory devices.

20. A memory module comprising:
means for storing data including primary data ports for transferring the data with a memory controller, and backup data ports for transferring the data with a non-volatile memory (NVM) data backup subsystem that is separate from the memory module;
wherein the memory module is configured to forward to the NVM data backup subsystem a signal received from the memory controller to backup the data stored in the means for storing data, and receive a backup command from the NVM data backup subsystem responsive to forwarding the signal, and
wherein the memory module is configured to reconfigure the primary data ports and the backup data ports of the means for storing data responsive to receiving the backup command from the NVM data backup subsystem such that the data is offloaded from the memory module to the NVM data backup subsystem via the backup data ports.

Assignees

• Rambus Inc

Inventors

• Shallal Aws
• Alvares Nigel
• Kochak Sarvagya

Classifications

• G11C14/0018 Primary

  whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor · CPC title

• G11C2207/2227

  Standby or low power modes · CPC title

• G11C5/04 Primary

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C11/005

  comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title