Memory module having volatile and non-volatile memory subsystems and method of operation

Patent metadata

Field	Value
Publication number	US-10198350-B2
Application number	US-201514706873-A
Country	US
Kind code	B2
Filing date	May 7, 2015
Priority date	Jul 28, 2011
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller reads first data from the non-volatile memory subsystem in response to a Flash access request received via the memory channel, and causes at least a portion of the first data to be written into the volatile memory subsystem in response to a dummy write memory command received via the C/A bus. The module control device includes status registers accessible by the computer system via the memory bus.

First claim

We claim:

1. A memory module for use in a computer system, the computer system including a memory controller coupled to the memory module via a memory channel, the memory channel including a data bus and a control/address (C/A) bus, comprising:
a volatile memory subsystem coupled to the memory channel, the volatile memory subsystem including a registered control device (RCD) configured to receive input C/A signals from the C/A bus and memory devices configured to perform memory operations in response to output C/A signals from the RCD that are derived from the input C/A signals;
a non-volatile memory subsystem; and
a module control device coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the memory channel, wherein the module control device is configured to perform a page-fault operation in response to a set of signals received from the memory channel indicating a non-volatile memory access request to transfer first data from the non-volatile memory subsystem to the volatile memory subsystem, the page fault operation including reading the first data from the non-volatile memory subsystem in response to the set of signals, and providing at least a portion of the first data to the volatile memory subsystem in response to a dummy write memory command received via the C/A bus, the dummy write memory command being received by both the module control device and the RCD and including a memory address related to the page-fault operation.

2. The memory module of claim 1 , further comprising buffer memory, wherein the module control device is further configured to, as part of the page fault operation, store the first data into the buffer memory after reading the first data from the non-volatile memory subsystem and send a read command to the buffer memory to cause the buffer memory to output another portion of the first data after receiving the dummy write memory command; wherein the volatile memory subsystem is configured to receive the at least a portion of the first data in response to the dummy write memory command, and wherein the volatile memory subsystem, the non-volatile memory subsystem, the module control device and the buffer memory are mounted on a same printed circuit board.

3. The memory module of claim 2 , wherein the module control device is configured to read second data from the volatile memory subsystem in response to the set of signals indicating the non-volatile memory access request, wherein the buffer memory includes a first memory and a second memory, wherein the module control device is further configured to write the first data into the first memory concurrently with writing the second data into the second memory.

4. The memory module of claim 3 , wherein the module control device is configured to perform error correction on the first data stored in the first memory by reading data from the first memory, performing error detection and correction on data read from the first memory, and storing corrected data back into the first memory, and wherein the module control device is further configured to transfer the second data from the second memory to the non-volatile memory subsystems concurrently with performing error correction on the first data stored in the first memory.

5. The memory module of claim 1 , wherein the set of signals indicating the non-volatile memory access request include a set of C/A signals received via the C/A bus and a set of data signals received via the data bus, the set of data signals including information about one or more locations in the non-volatile memory subsystem.

6. The memory module of claim 2 , wherein the module control device includes status registers accessible by the computer system via the memory channel, the status registers for storing therein status bits for the non-volatile memory access request, and wherein the module control device is further configured to, as part of the page fault operation, provide the status bits to the memory controller via the memory channel in response to a read command and a read address received from the memory controller, the read address being in an address space assigned to the status registers.

7. The memory module of claim 6 , wherein the status registers is further configured to store an ECC code associated with the status bits, and wherein the module control device provides the ECC code along with the status bits.

8. The memory module of claim 6 , wherein the status bits include information regarding an estimated wait time for the first data to be stored into the buffer memory.

9. The memory module of claim 1 , wherein the at least a portion of the first data includes a first portion of the first data, wherein the memory devices in the volatile memory subsystem include double data rate dynamic random access memory devices, wherein the memory module is configured to receive a normal write memory command via the C/A bus after receiving the dummy write memory command, and to receive write data via the data bus in response to the normal write memory command, and wherein the module control device is further configured to cause a second portion of the first data to be written into the volatile memory subsystem in response to another dummy write memory command received after the normal write memory command.

10. The memory module of claim 9 , further comprising a serial presence detect device coded with a memory density bigger than a memory density of the volatile memory subsystem thereby allowing for a non-volatile memory access address space that is outside a memory address space for the volatile memory subsystem, wherein the non-volatile memory access request includes an address in the non-volatile memory access address space.

11. A method of operating a memory module in a computer system, the computer system including a memory controller coupled to the memory module via a memory channel, the memory channel including a data bus and a control/address (C/A) bus, the method comprising:
receiving, by a module control device on the memory module, a set of signals from the memory controller via the memory channel; and
performing a page fault operation in response to the set of signals indicating a non-volatile memory access request to transfer first data from a non-volatile memory subsystem on the memory module to a volatile memory subsystem on the memory module, the page fault operation including:
reading first data from the non-volatile memory subsystem in response to receiving the set of signals;
receiving, by the module control device, a dummy write memory command via the C/A bus, the dummy write memory command including an address related to the page-fault operation; and
providing at least a portion of the first data to the volatile memory subsystem in response to the dummy write memory command, wherein the volatile memory subsystem includes a registered control device (RCD) configured to receive the dummy write memory command via the C/A bus, and wherein the volatile memory subsystem is configured to receive the at least a portion of the first data in response to the dummy write memory command.

12. The method of claim 11 , wherein the memory module further includes buffer memory, wherein the page-fault operation further includes: storing the first data into the buffer memory after reading the first data from the non-volatile memory subsystem, and causing the buffer memory to output another portion of the first data after receiving the dummy write memory command.

13. The method of claim 12 , wherein the buffer memory includes first memory and a second memory, the method further comprising:
reading second data from the volatile memory subsystem in respon

Assignees

• Netlist Inc

Inventors

• Lee Hyun

Classifications

• G11C7/1072

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G06F2212/7208

  Multiple device management, e.g. distributing data over multiple flash devices · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F2206/1014

  One time programmable [OTP] memory, e.g. PROM, WORM · CPC title

• G06F2212/313

  In storage device · CPC title