Memory module for platform with non-volatile storage

Patent metadata

Field	Value
Publication number	US-10839904-B2
Application number	US-201716467619-A
Country	US
Kind code	B2
Filing date	Nov 20, 2017
Priority date	Dec 9, 2016
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

A system that includes a non-volatile memory subsystem having non-volatile memory. The system also includes a plurality of memory modules that are separate from the non-volatile memory subsystem. Each memory module can include a plurality of random access memory packages where each first random access memory package includes a primary data port and a backup data port. Each memory module can include a storage interface circuit coupled to the backup data ports of the random access memory packages. The storage interface circuit offloads data from the memory module in the event of a power loss by receiving data from the backup data ports of the random access memory packages and transmitting the data to the non-volatile memory subsystem.

First claim

What is claimed is:

1. A system comprising:
a non-volatile memory (NVM) data backup subsystem including non-volatile memory; and
a plurality of memory modules that are separate from the NVM data backup subsystem, wherein a first memory module of the memory modules comprises:
a plurality of first random access memory packages, each first random access memory package including a primary data port and a backup data port; and
a first storage interface circuit coupled to the backup data ports of the first random access memory packages, the first storage interface circuit offloading data from the first memory module in the event of a power loss by receiving data from the backup data ports of the first random access memory packages and transmitting the data to the NVM data backup subsystem.

2. The system of claim 1 , wherein the first memory module comprises:
a data backup connector;
wherein the first storage interface circuit transmits the data to the NVM data backup subsystem via the data backup connector.

3. The system of claim 2 , wherein the data backup connector is a cable connector.

4. The system of claim 2 , wherein the data backup connector is a dual in line memory module edge connector.

5. The system of claim 1 , wherein the first memory module comprises:
an edge connector at an edge of the first memory module; and
a plurality of data buffer circuits to buffer data between the edge connector and the primary data ports of the first random access memory packages,
wherein the data buffer circuits are turned off while the storage interface circuit is offloading data.

6. The system of claim 1 , wherein clock synchronization circuits in the first random access memory packages are turned off while the storage interface circuit is offloading data.

7. The system of claim 1 , wherein the first storage interface circuit comprises a serializer circuit to serialize the data received from the backup data ports of the first random access memory packages into serialized data, wherein the data is transmitted to the NVM data backup subsystem is the serialized data.

8. The system of claim 1 , wherein each first random access memory package comprises:
a random access memory core; and
multiplexing circuitry that is coupled to the random access memory core through a data access path, the multiplexing circuitry selectively coupling one of the primary data port and the backup data port to the data access path at a time.

9. The system of claim 1 , wherein the first storage interface circuit restores the data to the first memory module when power is restored by receiving the data from the NVM data backup subsystem and writing the data to the backup data ports of the random access memory packages.

10. The system of claim 1 , wherein a second memory module of the memory modules comprises:
a plurality of second random access memory packages, each second random access memory package including a primary data port and a backup data port; and
a second storage interface circuit coupled to the backup data ports of the second random access memory packages, the second storage interface circuit offloading data from the second memory module in event of the power loss by receiving data from the backup data ports of the second random access memory packages and transmitting the data to the NVM data backup subsystem.

11. The system of claim 10 , wherein the non-volatile memory subsystem comprises:
a non-volatile memory device that includes the non-volatile memory; and
a central backup controller to receive the data from the first memory module and to receive the data from the second memory module, the central backup controller writing the data from the first memory module and the data from the second memory module to the non-volatile memory device.

12. A memory module comprising:
a plurality of random access memory packages, each including a primary data port and a backup data port; and
a storage interface circuit coupled to the backup data ports of the random access memory packages, the storage interface circuit to offload data from the memory module in the event of a power loss by receiving data from the backup data ports of the memory packages and transmitting the data to an external non-volatile memory (NVM) data backup subsystem that is separate from the memory module.

13. The memory module of claim 12 , wherein the memory module comprises:
a data backup connector;
wherein the storage interface circuit transmits the data to the external NVM data backup subsystem via the data backup connector.

14. The memory module of claim 13 , wherein the data backup connector is a ribbon cable connector.

15. The memory module of claim 13 , wherein the data backup connector is a dual in line memory module edge connector.

16. The memory module of claim 12 , further comprising:
an edge connector at an edge of the memory module; and
a plurality of data buffer circuits to buffer data between the edge connector and the primary data ports of the random access memory packages,
wherein the data buffer circuits are turned off while the storage interface circuit is offloading data.

17. The memory module of claim 12 , wherein a clock synchronization circuit in the random access memory packages is turned off while the storage interface circuit is offloading data.

18. The memory module of claim 12 , wherein the storage interface circuit comprises a serializer circuit to serialize the data received from the backup data ports of the random access memory packages into serialized data, wherein the data is transmitted to the external NVM data backup subsystem is the serialized data.

19. The memory module of claim 12 , wherein each random access memory package comprises:
a random access memory core; and
multiplexing circuitry that is coupled to the random access memory core through a data access path, the multiplexing circuitry selectively coupling one of the primary data port and the backup data port to the data access path at a time.

20. The memory module of claim 12 , wherein the storage interface circuit restores the data to the memory module when power is restored by receiving the data from the external NVM data backup subsystem and writing the data to the backup data ports of the random access memory packages.

Assignees

• Rambus Inc

Inventors

• Shallal Aws
• Alvares Nigel
• Kochak Sarvagya

Classifications

• G11C2207/2227

  Standby or low power modes · CPC title

• G11C5/04 Primary

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C5/00

  Details of stores covered by group G11C11/00 · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title