Non-volatile memory storage for multi-channel memory system

Patent metadata

Field	Value
Publication number	US-9436600-B2
Application number	US-201414302292-A
Country	US
Kind code	B2
Filing date	Jun 11, 2014
Priority date	Jun 11, 2013
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals. The NV controller and the non-volatile memory can be mounted on the motherboard.

First claim

What is claimed is:

1. A method for monitoring memory access operations in a computer system having a memory controller, the method comprising:
coupling the memory controller of the computer system to an interface via a set of data lines and a set of address and control signal lines;
coupling the interface to a first memory channel via a first set of data lines and a first set of address and control signal lines, wherein a first volatile memory subsystem is coupled to the interface via the first memory channel, the first volatile memory subsystem communicates data with the memory controller of the computer system via the interface using the first set of data lines;
coupling the interface to a second memory channel via a second set of data lines and a second set of address and control signal lines, wherein a second volatile memory subsystem is coupled to the interface via the second memory channel, the second volatile memory subsystem communicates data with the memory controller of the computer system via the interface using the second set of data lines;
coupling the interface to a nonvolatile memory subsystem, the nonvolatile memory subsystem including an NV (non-volatile) controller and at least one nonvolatile memory element;
monitoring each of the first and second memory channels to detect one or more memory access operations from the memory controller of the computer system to at least one predetermined address range of the first or second volatile memory subsystems; and
capturing a copy of data associated with the one or more memory access operations.

2. The method of claim 1 , further comprising:
storing the captured copy of data associated with the one or more memory access operations in the at least one nonvolatile memory element.

3. The method of claim 1 , wherein the one or more memory access operations include one or more data write operations performed by the memory controller of the computer system to one or more of the first or second volatile memory subsystems.

4. The method of claim 1 , wherein (i) the first memory channel includes a first volatile memory module comprising the first volatile memory subsystem, (ii) the second memory channel includes a second volatile memory module comprising the second volatile memory subsystem, and (iii) the one or more memory access operations include one or more memory access operations performed by the memory controller to one or more of the first or second memory modules.

5. The method of claim 1 , wherein the capturing a copy of data associated with the one or more memory access operations further comprising:
generating a trigger signal; and
capturing a copy of data associated with the one or more memory access operations in response to the trigger signal.

6. The method of claim 5 , wherein the generating a trigger signal further comprises:
generating a trigger signal upon detecting the occurrence of one or more of a power interruption, a power failure, a power reduction, a system hang-up, a request by the host computer system, the host computer system voltage going below a certain threshold voltage, the host computer system voltage going above a certain threshold voltage, the host computer system voltage being below a first threshold voltage and above a second threshold voltage, and a reboot condition.

7. A method for performing memory access operations in a computer system having first and second volatile memory modules, the computer system including a memory controller configured to independently access the first and second volatile memory modules via respective first and second memory channels, the first volatile memory module being coupled to the first memory channel via a first set of data, address and control signal lines, the second volatile memory module being coupled to the second memory channel via a second set of data, address and control signal lines, the method comprising:
monitoring, using at least one NV (non-volatile) controller, the first and second memory channels to detect memory access operations;
capturing a copy of data associated with a first memory access operation to a first address range using a first one of the at least one NV controller upon detection of the first memory access operation, wherein the first memory access operation allows data to be communicated between the memory controller and the first volatile memory module using the first memory channel; and
capturing a copy of data associated with a second memory access operation to a second address range using a second one of the at least one NV controller upon detection of the second memory access operation, wherein the second memory access operation allows data to be communicated between the memory controller and the second volatile memory module using the second memory channel.

8. The method of claim 7 , further comprising: storing the copy of data associated with the first memory access operation and the copy of data associated with the second memory access operation in a nonvolatile memory subsystem.

9. The method of claim 7 , wherein the first address range is associated with the memory address space of the first volatile memory module, and the second address range is associated with the memory address space of the second volatile memory module.

10. The method of claim 8 , further comprising:
detecting a trigger condition; and
restoring data from the nonvolatile memory subsystem to at least one of the first and second volatile memory modules in response to the trigger condition.

11. The method of claim 8 , wherein the nonvolatile memory subsystem comprises one or more cache memory coupled to the NV controller and the first and second memory channels; and wherein storing the copy of data associated with the first or second memory access operation comprises storing the copy of data associated with the first or second memory access operation into the one or more cache memory.

12. The method of claim 11 , further comprising: using the NV controller to manage data communication between the one or more cache memory and the nonvolatile memory subsystem.

13. The method of claim 7 , further comprising: storing the copy of data associated with the first or second memory access operation into one or more cache memory coupled to the NV controller.

14. The method of claim 13 , further comprising: using the NV controller to manage data communication between the one or more cache memory and the nonvolatile memory subsystem.

15. A method for operating a nonvolatile memory subsystem having an NV (non-volatile) controller and one or more nonvolatile memory modules, the method comprising:
using at least two memory channels to couple a host computer system to a volatile memory subsystem, wherein the at least two memory channels are independently accessible by the host computer system;
coupling the NV controller to the one or more nonvolatile memory modules;
coupling the NV controller to the at least two memory channels, wherein each one of the at least two memory channels includes address, data and control signals;
monitoring each one of the at least two memory channels for the occurrence of one or more memory access operations to the volatile memory subsystem; and
capturing a copy of data associated with a first memory access operation of the one or more memory access operations.

16. The method of claim 15 , further comprising:
storing the copy of data associated with the first memory access operation into the one or more nonvolatile memory modules.

17. The method of claim 15 , wherein the one or more memory access operations include

Assignees

• Netlist Inc
• Svic No 28 New Tech Business Invest L L P

Inventors

• Lee Hyun

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F2212/214

  Solid state disk · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title