Method of manufacturing a semiconductor device and apparatus for manufacturing the semiconductor device

US11320747B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11320747-B2
Application numberUS-202017121542-A
CountryUS
Kind codeB2
Filing dateDec 14, 2020
Priority dateJul 31, 2018
Publication dateMay 3, 2022
Grant dateMay 3, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Photolithography apparatus includes a radiation source, a mask to modify radiation from the radiation source so the radiation exposes photoresist layer disposed on a semiconductor substrate in patternwise manner, a wafer stage, and a controller. The wafer stage supports the semiconductor substrate. The controller determines target total exposure dose for the photoresist layer and target focus position for the photoresist layer; and controls exposure of first portion of the photoresist layer to first exposure dose of radiation at first focus position using first portion of the mask, moving the semiconductor substrate relative to the mask; and exposure of the first portion of the photoresist layer to second exposure dose of radiation using second portion of the mask at second focus position, and exposure of second portion of the photoresist layer to the second exposure dose at the second focus position using the first portion of the mask.

First claim

Opening claim text (preview).

What is claimed is: 1. A photolithography apparatus, comprising: a radiation source; a mask configured to modify radiation from the radiation source so that the radiation exposes a photoresist layer disposed on a semiconductor substrate in a patternwise manner; a wafer stage configured to support the semiconductor substrate; and a controller, wherein the controller is configured to: determine a target total exposure dose for the photoresist layer; determine a target focus position for the photoresist layer; control an exposure of a first portion of the photoresist layer to a first exposure dose of radiation at a first focus position using a first portion of the mask; control moving of the semiconductor substrate relative to the mask; and control an exposure of the first portion of the photoresist layer to a second exposure dose of radiation using a second portion of the mask at a second focus position, and an exposure of a second portion of the photoresist layer to the second exposure dose at the second focus position using the first portion of the mask. 2. The photolithography apparatus of claim 1 , wherein the mask is a reflective extreme ultraviolet mask. 3. The photolithography apparatus of claim 1 , wherein the wafer stage is further configured to move closer to and further away from the mask. 4. The photolithography apparatus of claim 1 , wherein the wafer stage is further configured to move laterally with respect to the mask. 5. The photolithography apparatus of claim 1 , wherein the controller is further configured to control movement of the wafer stage. 6. The photolithography apparatus of claim 1 , wherein the controller is further configured to control an exposure of the first portion of the photoresist layer to a third exposure dose of radiation at a third focus position using a third portion of the mask, an exposure of the second portion of the photoresist layer to the third exposure dose of radiation at the third focus position using the second portion of the mask, and an exposure of a third portion of the photoresist layer to the third exposure dose at the third focus position using the first portion of the mask. 7. The photolithography apparatus of claim 6 , wherein the controller is further configured to control an exposure of the first portion of the photoresist layer to a fourth exposure dose of extreme ultraviolet radiation at a fourth focus position using a fourth portion of the mask, an exposure of the second portion of the photoresist layer to the fourth exposure dose of extreme ultraviolet radiation at the fourth focus position using the third portion of the mask, an exposure of a third portion of the photoresist layer to the fourth exposure dose at the fourth focus position using the second portion of the mask, and an exposure of a fourth portion of the photoresist layer to the fourth exposure dose of extreme ultraviolet radiation at the fourth focus position using the first portion of the mask. 8. The photolithography apparatus of claim 7 , wherein the first portion of the mask, the second portion of the mask, the third portion of the mask, and the fourth portion of the mask each have a same pattern. 9. A method of manufacturing a semiconductor device, comprising: placing a semiconductor substrate on a wafer stage, wherein the semiconductor substrate has a photoresist layer disposed thereon; determining a target total exposure dose for the photoresist layer; determining a target distance separating the photoresist layer from an extreme ultraviolet mask; exposing a first portion of the photoresist layer to a first exposure dose of extreme ultraviolet radiation using a first portion of the extreme ultraviolet mask, wherein the photoresist layer and the extreme ultraviolet mask are separated by a first distance; a first lateral stepping of the semiconductor substrate relative to the extreme ultraviolet mask; changing a distance between the semiconductor substrate and the extreme ultraviolet mask so that the photoresist layer and the extreme ultraviolet mask are separated by a second distance; and exposing the first portion of the photoresist layer to a second exposure dose of extreme ultraviolet radiation using a second portion of the mask, and exposing a second portion of the photoresist layer to the second exposure dose using the first portion of the mask. 10. The method according to claim 9 , further comprising: a second lateral stepping of the semiconductor substrate relative to the mask; changing the distance between the semiconductor substrate and the mask so that the photoresist layer and the mask are separated by a third distance; and exposing the first portion of the photoresist layer to a third exposure dose of extreme ultraviolet radiation using a third portion of the mask, exposing the second portion of the photoresist layer to the third exposure dose of extreme ultraviolet radiation using the second portion of the mask, and exposing a third portion of the photoresist layer to the third exposure dose using the first portion of the mask. 11. The method according to claim 10 , further comprising: a third lateral stepping of the semiconductor substrate relative to the mask; changing the distance between the semiconductor substrate and the mask so that the photoresist layer and the extreme ultraviolet mask are separated by a fourth distance; and exposing the first portion of the photoresist layer to a fourth exposure dose of extreme ultraviolet radiation using a fourth portion of the mask, exposing the second portion of the photoresist layer to the fourth exposure dose of extreme ultraviolet radiation using the third portion of the mask, exposing a third portion of the photoresist layer to the fourth exposure dose using the second portion of the mask, and exposing a fourth portion of the photoresist layer to the fourth exposure dose of extreme ultraviolet radiation using the first portion of the mask. 12. The method according to claim 11 , wherein the first portion of the mask, the second portion of the mask, the third portion of the mask, and the fourth portion of the mask each have a same pattern. 13. The method according to claim 11 , wherein the first distance is greater than the target distance, the second distance is less than the target distance, the third distance is greater than the target distance, and the fourth distance is less than the target distance. 14. The method according to claim 11 , wherein the distance between the photoresist layer and the mask is changed by raising or lowering the wafer stage. 15. The method according to claim 11 , wherein a total of all the exposure doses received by each portion of the photoresist layer is equal to the target expose dose. 16. A method of manufacturing a semiconductor device, comprising in sequence: placing a semiconductor substrate on a wafer stage, wherein the semiconductor substrate has a photoresist layer disposed thereon; exposing a first portion of the photoresist layer to a first exposure dose of extreme ultraviolet radiation using a first portion of an extreme ultraviolet mask, moving the semiconductor substrate relative to the extreme ultraviolet mask; exposing the first portion of the photoresist layer to a second exposure dose of extreme ultraviolet radiation using a second portion of the mask, and exposing a second portion of the photoresist layer to the second exposure dose using the first portion of the mask; moving the semiconductor substrate relative to the extreme ultraviolet mask; exposing the first portion of the photoresist layer to a third exposure dose of ex

Assignees

Inventors

Classifications

  • Dose control, i.e. achievement of a desired dose · CPC title

  • Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure · CPC title

  • comprising an imagewise exposure to electromagnetic radiation or corpuscular radiation · CPC title

  • G03F7/22Primary

    Exposing sequentially with the same light pattern different positions of the same surface {(G03F7/70 takes precedence)} · CPC title

  • characterised by the use of a particular light source, e.g. fluorescent lamps or deep UV light · CPC title

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What does patent US11320747B2 cover?
Photolithography apparatus includes a radiation source, a mask to modify radiation from the radiation source so the radiation exposes photoresist layer disposed on a semiconductor substrate in patternwise manner, a wafer stage, and a controller. The wafer stage supports the semiconductor substrate. The controller determines target total exposure dose for the photoresist layer and target focus p…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification G03F7/22. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 03 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).