Structure facilitating optically checking via formation

Patent metadata

Field	Value
Publication number	US-11320387-B2
Application number	US-201816203195-A
Country	US
Kind code	B2
Filing date	Nov 28, 2018
Priority date	Nov 28, 2018
Publication date	May 3, 2022
Grant date	May 3, 2022

Abstract

Techniques regarding one or more structures for checking the via formation are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a microfluidic channel positioned on a silicon substrate. The apparatus can also comprise a pattern of material comprised within the microfluidic channel and positioned on a surface of the silicon substrate. Further, the pattern of material can define a future location of a through-silicon via. An advantage of such an apparatus can be that the pattern of material can facilitate checking whether the through-silicon via is fully or partially formed.

First claim

What is claimed is:

1. An apparatus, comprising:
a microfluidic channel positioned on a silicon substrate; and
a pattern of material comprised within the microfluidic channel and positioned on a surface of the silicon substrate, wherein the pattern of material is aligned with and formed within the formation area defines a location of a through-silicon via, wherein the pattern of material is optically visible against the surface of the silicon substrate based on contrast differences caused by thickness and edge contours of the pattern as compared to the surface of the silicon substrate, and wherein the through-silicon via extends through a second surface of the silicon substrate towards the pattern of material.

2. The apparatus of claim 1 , wherein the pattern of material is lithographically defined from the silicon substrate, and wherein the silicon substrate is transparent.

3. The apparatus of claim 2 , wherein the pattern of material is a relief formed from the silicon substrate.

4. The apparatus of claim 2 , wherein the pattern of material is etched into the silicon substrate.

5. The apparatus of claim 1 , further comprising:
a sealing layer positioned on the silicon substrate, wherein the sealing layer and the silicon substrate together encapsulate the microfluidic channel.

6. The apparatus of claim 5 , wherein the sealing layer is positioned on a first side of the silicon substrate, wherein the through-silicon via extends from a second side of the silicon substrate towards the pattern of material and wherein the first side is opposite the second side.

7. The apparatus of claim 1 , wherein the pattern of material divides an area of the silicon substrate into a plurality of sectors.

8. A computer-implemented method, comprising:
capturing, by a system operably coupled to a processor, an image of a first surface of a substrate; and
comparing, by the system, the image to a reference image of a pattern of material to determine a formation progress of a via formed into the substrate, wherein the via extends from a second surface of the substrate towards the first surface.

9. The computer-implemented method of claim 8 , further comprising:
determining, by the system, that the pattern of material is absent from the first surface based on the comparing; and
determining, by the system, that the via is a fully formed via based on the determining that the pattern of material is absent from the first surface.

10. The computer-implemented method of claim 8 , further comprising:
determining, by the system, that the pattern of material is at least partially present on the first surface based on the comparing; and
determining, by the system, that the via is a partially formed via based on the determining that the pattern of material is at least partially present on the first surface.

11. The computer-implemented method of claim 10 , further comprising:
etching the via to increase a dimension of the via.

12. The computer-implemented method of claim 8 , wherein the substrate is a silicon substrate, wherein the pattern of material is a pattern of silicon material, and wherein the via is a silicon-through via.

13. A method, comprising:
identifying a location on a substrate where a via will be formed; and
fabricating a pattern of material at the location to form an etch check, wherein a presence of the etch check on the substrate subsequent to an etching of the via into the substrate indicates that the via is partially etched.

14. The method of claim 13 , wherein the etch check is confined within the location on the substrate where the via will be formed.

15. The method of claim 14 , wherein an edge contour of the pattern of material visually distinguishes the pattern of material from the substrate.

16. The method of claim 13 , further comprising:
lithographically defining the pattern of material in relief from the substrate, wherein the substrate is a silicon substrate, and wherein the via is a through-silicon via.

17. The method of claim 13 , further comprising:
etching the pattern of material into the substrate, wherein the substrate is a silicon substrate, and wherein the via is a through-silicon via.

18. The method of claim 13 , further comprising:
optically inspecting the location on the substrate subsequent to the etching of the via to determine whether the etch check is present on the substrate.

Assignees

• IBM

Inventors

• Wunsch Benjamin
• Kim Sung-Cheol
• Gifford Stacey
• Smith Joshua T

Classifications

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P72/50

  for positioning, orientation or alignment · CPC title

• G01N2201/06113

  Coherent sources; lasers · CPC title

• H01J37/32963

  End-point detection · CPC title

• G01N21/9501 Primary

  Semiconductor wafers (manufacturing processes per se of semiconductor devices implementing a measuring step H10P74/20) · CPC title