Delay based comparator

Patent metadata

Field	Value
Publication number	US-11316505-B2
Application number	US-202117181073-A
Country	US
Kind code	B2
Filing date	Feb 22, 2021
Priority date	Dec 29, 2017
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

An analog to digital converter (ADC) comprising: a delay circuit having a complementary signal output; a first comparator having an input coupled to the complementary signal output of the delay circuit, the first comparator having a first output and a second output; a first dummy comparator having a first dummy input coupled to the first output and a second dummy input coupled to the second output, the first dummy comparator having a dummy output; a first interpolation comparator having an interpolation output and a first interpolation input coupled to the first output; a second dummy comparator having an input coupled to the interpolation output; and a second interpolation comparator having a second interpolation input and a third interpolation input, the second interpolation input coupled to the interpolation output and the third interpolation input coupled to the dummy output.

First claim

What is claimed is:

1. An analog to digital converter (ADC) comprising:
a delay circuit having a complementary signal output;
a first comparator having an input coupled to the complementary signal output of the delay circuit, the first comparator having a first output and a second output;
a first dummy comparator having a first dummy input coupled to the first output and a second dummy input coupled to the second output, the first dummy comparator having a dummy output;
a first interpolation comparator having an interpolation output and a first interpolation input coupled to the first output;
a second dummy comparator having an input coupled to the interpolation output; and
a second interpolation comparator having a second interpolation input and a third interpolation input, the second interpolation input coupled to the interpolation output and the third interpolation input coupled to the dummy output.

2. The ADC of claim 1 , wherein the delay comparator includes at least two inputs.

3. The ADC of claim 2 , wherein the delay comparator includes complementary input signal inputs and complementary reference signal inputs.

4. The ADC of claim 2 , wherein the delay comparator includes a clock input.

5. The ADC of claim 3 , wherein the complementary signal output is comprised of a first signal output and a second signal output that is the complement of the first signal output.

6. The ADC of claim 5 , wherein the complementary input signals includes a first input signal and a second input signal that is the complement of the first input signal, and the complementary reference signal includes a first reference signal and a second reference signal that is the complement of the first reference signal.

7. The ADC of claim 6 , wherein the first signal output precedes the second signal output responsive to the difference of the first input signal and the second input signal being greater than the difference of the first reference signal and the second reference signal.

8. The ADC of claim 6 , wherein the second signal output precedes the first signal output responsive to the difference of the first input signal and the second input signal being less than the difference of the first reference signal and the second reference signal.

9. An analog to digital converter (ADC) comprising:
a first delay circuit having a first complementary input operable to receive a complementary analog input signal, a second complementary input operable to receive a first complementary reference voltage, and a first complementary signal output comprised of a first signal output and a second signal output that is the complement of the first signal output;
a second delay circuit having a third complementary input operable to receive the complementary analog input signal, a fourth complementary input operable to receive a second complementary reference voltage that is different than the first complementary reference voltage, and a second complementary signal output;
a first comparator having an input coupled to the first complementary signal output, the first comparator having a first comparator output;
a second comparator having an input coupled to the second complementary signal output, the second comparator having a second comparator output;
a first dummy comparator coupled to the first comparator output;
a second dummy comparator coupled to the second comparator output;
a first interpolation comparator having a first interpolation input coupled to the first comparator output and a second interpolation input coupled to the second comparator output; and
wherein a signal at the first signal output precedes or is delayed with respect to a signal at the second signal output responsive to whether the complementary analog input signal is larger than or smaller than the first complementary reference voltage.

10. The ADC of claim 9 , wherein the first and second delay circuits include a clock input.

11. The ADC of claim 9 , wherein the complementary analog input signals includes a first input signal and a second input signal that is the complement of the first input signal, and the first complementary reference signal includes a first reference signal and a second reference signal that is the complement of the first reference signal.

12. The ADC of claim 11 , wherein the first signal output precedes the second signal output responsive to the difference of the first input signal and the second input signal being greater than the difference of the first reference signal and the second reference signal.

13. The ADC of claim 12 , wherein the second signal output precedes the first signal output responsive to the difference of the first input signal and the second input signal being less than the difference of the first reference signal and the second reference signal.

Assignees

• Texas Instruments Inc

Inventors

• Soundararajan Rishi
• Pentakota Visvesvaraya

Classifications

• H03K5/2481 Primary

  with at least one differential stage · CPC title

• H03K3/356139

  with synchronous operation · CPC title

• H03M1/50

  with intermediate conversion to time interval (H03M1/64 takes precedence) · CPC title

• H03M1/46

  with digital/analogue converter for supplying reference values to converter · CPC title

• H03K2005/00215

  where the conduction path of multiple FET's is in parallel or in series, all having the same gate control · CPC title