Analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-9742424-B2
Application number	US-201715400093-A
Country	US
Kind code	B2
Filing date	Jan 6, 2017
Priority date	Jan 7, 2016
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

An analog-to-digital converter (ADC) is provided, having two comparators, two digital-to-analog converters (DACs), and an adder circuit. The ADC receives an input value and, over a plurality of conversion cycles of the ADC, generates an output value representative of the input value. Each respective DAC generates a plurality of threshold levels, which are defined, at least in part, by predetermined redundancy levels that are binary-scaled. The comparator arrangement provides an output code in a respective conversion cycle and, for at least two adjacent conversion cycles, the two comparators collectively provide 2-bit output codes. The adder circuit provides a plurality of output bits of the output value, and is capable of overlapping and adding a first significant bit of the 2-bit output code provided for a predetermined conversion cycle with a second significant bit of the 2-bit output code provided for a previous conversion cycle to generate one output bit.

First claim

The invention claimed is:

1. An analog-to-digital converter (ADC) comprising:
a comparator arrangement comprising two comparators;
a digital-to-analog converter (DAC) arrangement comprising two DACs, wherein each DAC of the two DACs is connected to a respective comparator of the two comparators; and
an adder circuit connected to the comparator arrangement,
wherein the ADC is configured to receive an input value and further configured, over a plurality of conversion cycles of the ADC, to generate an output value representative of the input value,
wherein, for each respective DAC, the DAC is configured to sample the input value, and to generate a plurality of threshold levels over the plurality of conversion cycles, the sampled input value and the plurality of threshold levels to be received by the respective comparator, wherein the plurality of threshold levels are defined, at least in part, by predetermined redundancy levels that are binary-scaled over the plurality of conversion cycles and generated by the DAC, and, wherein a respective threshold level of the plurality of threshold levels is associated with a respective conversion cycle of the plurality of conversion cycles,
wherein the comparator arrangement is configured to provide an output code for the respective conversion cycle based on the sampled input value and the respective threshold level associated with at least one of the two comparators, and, wherein, for at least two adjacent conversion cycles of the plurality of conversion cycles, the two comparators are adapted to collectively provide output codes having two bits based on the sampled input value and the respective threshold levels associated with the two comparators, wherein the respective threshold levels for a predetermined conversion cycle of the at least two adjacent conversion cycles is dependent on the output code having two bits of a previous conversion cycle of the at least two adjacent conversion cycles, and
wherein the adder circuit is configured to provide a plurality of output bits corresponding to the output value, wherein the adder circuit is capable of overlapping and adding a first significant bit of the output code having two bits provided for the predetermined conversion cycle with a second significant bit of the output code having two bits provided for the previous conversion cycle to generate one output bit of the plurality of output bits.

2. The ADC as claimed in claim 1 ,
wherein, for an initial conversion cycle of the plurality of conversion cycles, the comparator arrangement is configurable to provide the output code having one bit, and
wherein, for each of remaining conversion cycles of the plurality of conversion cycles, the two comparators are adaptable to collectively provide the output code having two bits.

3. The ADC as claimed in claim 1 ,
wherein, for an initial conversion cycle of the plurality of conversion cycles, the comparator arrangement is configurable to be a 1 bit/cycle comparator arrangement, and
wherein, for each of remaining conversion cycles of the plurality of conversion cycles, the comparator arrangement is configurable to be a 1.5 bits/cycle comparator arrangement.

4. The ADC as claimed in claim 3 , wherein the comparator arrangement is configurable to be a 1.5 bits/cycle comparator arrangement for each of all remaining conversion cycles of the plurality of conversion cycles.

5. The ADC as claimed in claim 1 , wherein the ADC is adaptable to enable one of the two comparators for an initial conversion cycle of the plurality of conversion cycles, and to enable both of the two comparators for each of remaining conversion cycles of the plurality of conversion cycles.

6. The ADC as claimed in claim 1 , wherein the ADC is configured to provide the output code for an initial conversion cycle of the plurality of conversion cycles as an output most significant bit corresponding to the output value.

7. The ADC as claimed in claim 1 , wherein the threshold level for an initial conversion cycle of the plurality of conversion cycles is free of a predetermined redundancy level.

8. The ADC as claimed in claim 1 , wherein the predetermined redundancy levels defining the respective threshold levels associated with the two DACs for the respective conversion cycle are of opposite signs.

9. The ADC as claimed in claim 1 , wherein each DAC of the two DACs comprises at least one capacitive DAC arrangement connected to the respective comparator, the at least one capacitive DAC arrangement comprising a plurality of binary-weighted capacitors.

10. The ADC as claimed in claim 9 ,
wherein each comparator of the two comparators comprises a first input terminal and a second input terminal, and
wherein the at least one capacitive DAC arrangement of the respective DAC is connected to the first input terminal of the respective comparator.

11. The ADC as claimed in claim 9 ,
wherein each comparator of the two comparators comprises a first input terminal and a second input terminal,
wherein the at least one capacitive DAC arrangement of each DAC comprises:
a first capacitive DAC arrangement comprising a first plurality of binary-weighted capacitors; and
a second capacitive DAC arrangement comprising a second plurality of binary-weighted capacitors,

wherein the first capacitive DAC arrangement of the respective DAC is connected to the first input terminal of the respective comparator, and
wherein the second capacitive DAC arrangement of the respective DAC is connected to the second input terminal of the respective comparator.

12. The ADC as claimed in claim 9 , wherein, for generating the respective threshold level for the respective conversion cycle, and dependent on the output code of a preceding conversion cycle, the at least one capacitive DAC arrangement of the respective DAC is configured to selectively switch to at least one of a predetermined common mode voltage, a first reference voltage or a second reference voltage.

13. The ADC as claimed in claim 12 , wherein, for generating the predetermined redundancy levels for defining the respective threshold levels associated with the two comparators for the respective conversion cycle, the at least one capacitive DAC arrangement of one of the two DACs is further configured to sample a first fraction of the first reference voltage and the at least one capacitive DAC arrangement of another of the two DACs is further configured to sample a second fraction of the first reference voltage.

14. The ADC as claimed in claim 13 ,
wherein, for generating the respective threshold levels for the respective conversion cycle, at least one binary-weighted capacitor of the plurality of binary-weighted capacitors of the respective DAC is configured to selectively switch to at least one of the predetermined common mode voltage, the first reference voltage or the second reference voltage, and
wherein, for generating the predetermined redundancy levels for defining the respective threshold levels associated with the two comparators for the respective conversion cycle, another binary-weighted capacitor of the plurality of binary-weighted capacitors adjacent to and of a lower weightage than the at least one binary-weighted capacitor is configured, for one of the two DACs, to sample the first fraction of the first reference voltage, and for the other of the two DACs, to sample the second fraction of the first reference voltage.

15. The ADC as claimed in claim 1 , wherein, for each conversion cycle starting from a third conversion cycle of the plurality of conversion cycles and ending in a final conversion cycle of the plurality of convers

Assignees

• Univ Nanyang Tech

Inventors

• Sharma Sunny
• Boon Chirn Chye

Classifications

• H03M1/46 Primary

  with digital/analogue converter for supplying reference values to converter · CPC title

• H03M1/1245 Primary

  Details of sampling arrangements or methods · CPC title

• H03M1/1009

  Calibration · CPC title

• H03M1/069

  by range overlap between successive stages or steps · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title