3-dimensional arrays of NOR-type memory strings

Patent metadata

Field	Value
Publication number	US-11315645-B2
Application number	US-202016820209-A
Country	US
Kind code	B2
Filing date	Mar 16, 2020
Priority date	Sep 30, 2015
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

Multi-gate NOR flash thin-film transistor (TFT) string arrays are organized as 3-dimensional stacks of active strips. Each active strip includes a shared source sublayer and a shared drain sublayer that is connected to substrate circuits. Data storage in the active strip is provided by charge-storage elements between the active strip and a multiplicity of control gates provided by adjacent local word-lines. The parasitic capacitance of each active strip is used to eliminate hard-wire ground connection to the shared source making it a semi-floating, or virtual source. Pre-charge voltages temporarily supplied from the substrate through a single port per active strip provide the appropriate voltages on the source and drain required during read, program, program-inhibit and erase operations. TFTs on multiple active strips can be pre-charged separately and then read, programmed or erased together in a massively parallel operation.

First claim

I claim:

1. A memory circuit, comprising:
a semiconductor substrate having a substantially planar surface and including circuitry formed therein and thereon;
a dielectric layer formed over the planar surface of the semiconductor substrate;
a semiconductor structure formed over the dielectric layer, comprising a first semiconductor sublayer of a first conductivity type provided between a second and a third semiconductor sublayers each of a second conductivity type, the first semiconductor sublayer having a first portion and a second portion that are isolated from each other by a non-conductive material, wherein the first, the second and third semiconductor sublayers provide the semiconductor structure a sidewall;
a conductor substantially outside the semiconductor structure substantially aligned with a portion of the first semiconductor sublayer; and
a charge-storage layer provided over the sidewall of the semiconductor structure between the conductor and the aligned portion of the semiconductor sublayer, wherein the first, second and third semiconductor sublayers providing, respectively, channel, source and drain regions of a thin-film storage transistor, wherein the conductor provides a gate electrode to the thin-film storage transistor, and wherein one of the second and third semiconductor sublayers is electrically isolated relative to the circuitry formed in the semiconductor substrate, except when the channel region is rendered conducting.

2. The memory circuit of claim 1 , wherein a separation between the second and third semiconductor sublayers has a thickness substantially defined by the non-conductive material, and wherein the first semiconductor sublayer is provided after at least a portion of the non-conductive material is removed from between the second and third semiconductor sublayers.

3. The memory circuit of claim 2 , wherein a portion of the non-conductive material remains between the second and third semiconductor sublayers to provide mechanical support and isolation.

4. The memory circuit of claim 1 , further comprising interconnect conductors embedded in the dielectric layer to interconnect the thin-film storage transistor and the circuitry at the planar surface of the semiconductor substrate.

5. The memory circuit of claim 4 , further comprising buried contacts formed in the dielectric layer to electrically connect the other one of the second and third semiconductor sublayers to the circuitry.

6. The memory circuit of claim 1 , further comprising a dopant diffusion-blocking layer between the first semiconductor sublayer and one or both of the second and the third semiconductor sublayer.

7. The memory circuit of claim 1 , wherein the charge-storage layer comprises a tunnel dielectric film and one or more layers of charge-trapping material each selected from silicon nitride, silicon-rich silicon nitride, silicon oxide, nanocrystals, nanodots embedded in a thin dielectric film, or isolated floating gates, wherein each layer of charge-trapping material is being provided between blocking dielectric films each selected from a silicon dioxide film, an ONO layer, a high dielectric constant film of materials including aluminum oxide, hafnium oxide or some combination thereof.

8. The memory circuit of claim 7 , wherein the tunnel dielectric layer comprises one or more of a silicon dioxide layer, a silicon oxide-silicon nitride-silicon oxide (“ONO”) triple layer, a bandgap engineered dielectric and a silicon nitride layer.

9. A memory circuit, comprising:
a semiconductor substrate having a substantially planar surface and including circuitry formed therein and thereon; and
a dielectric layer formed over the planar surface of the semiconductor substrate; and
a semiconductor structure formed over the dielectric layer, comprising a first semiconductor sublayer of a first conductivity type provided between a second and a third semiconductor sublayers each of a second conductivity type, the first semiconductor sublayer having a first portion and a second portion that are isolated from each other by a non-conductive material, wherein the first, the second and third semiconductor sublayers provide the semiconductor structure a sidewall;
a conductor substantially outside the semiconductor structure substantially aligned with a portion of the first semiconductor sublayer; and
a charge-storage layer provided over the sidewall of the semiconductor structure between the conductor and the aligned portion of the semiconductor sublayer, wherein the first, second and third semiconductor sublayers providing, respectively, channel, source and drain regions of a thin-film storage transistor, wherein the conductor provides a gate electrode to the thin-film storage transistor, and wherein one of the second and third semiconductor sublayers is electrically floating relative to the circuitry formed in the semiconductor substrate, except when the channel region is rendered conducting.

10. The memory circuit of claim 9 , wherein the first semiconductor sublayer provides a covering layer that defines a portion of a cavity inside the semiconductor structure.

11. The memory circuit of claim 10 , wherein a separation between the second and third semiconductor sublayers has a thickness substantially defined by the non-conductive material, and wherein the first semiconductor sublayer is provided after removal of at least a portion of the the non-conductive material is removed from between the second and third semiconductor sublayers.

12. The memory circuit of claim 11 , wherein a portion of the semiconductor material remains between the second and third semiconductor sublayers to provide mechanical support.

13. The memory circuit of claim 9 , further comprising interconnect conductors embedded in the dielectic layer to interconnect the thin-film storage transistor and the circuitry at the planar surface of the semiconductor substrate.

14. The memory circuit of claim 13 , further comprising buried contacts formed in the dielectric layer to electrically connect the other one of the second and third semiconductor sublayers.

15. The memory circuit of claim 9 , further comprising a dopant diffusion-blocking layer between the first semiconductor sublayer and one or both of the second and the third semiconductor sublayer.

16. The memory circuit of claim 9 , wherein the charge-storage layer comprises one or more layers of charge-trapping material selected form silicon nitride, silicon-rich silicon nitride, silicon oxide, nanocrystals, nanodots embedded in a thin dielectric film, or isolated floating gates, wherein each layer of charge-trapping material being provided between one or more layers of a dielectric material selected from the group consisting of silicon oxide, high dielectric-constant films of aluminum oxide or hafnium oxide, and bandgap engineered dielectrics.

17. The memory circuit of claim 16 , wherein the charge-trapping layer further comprises a blocking dielectric film selected from an ONO layer, a high dielectric constant film of materials including aluminum oxide, hafnium oxide or some combination thereof.

18. The memory circuit of claim 9 , wherein the charge storage material comprises a tunnel dielectric film.

19. The memory circuit of claim 18 , wherein the tunnel dielectric layer comprises one or more of: a silicon dioxide layer, a silicon oxide-silicon nitride-silicon oxide (“ONO”) triple layer, a bandgap engineered dielectric and a silicon nitride layer.

20. A memory circuit, comprising:
a semiconductor substrate having a substa

Assignees

• Sunrise Memory Corp

Inventors

• Harari Eli

Classifications

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D62/292

  Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512) · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D30/6723

  having light shields · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title