Arithmetic processing apparatus, and cache memory control device and cache memory control method
US-9251084-B2 · Feb 2, 2016 · US
US9400752B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-9400752-B1 |
| Application number | US-201615086546-A |
| Country | US |
| Kind code | B1 |
| Filing date | Mar 31, 2016 |
| Priority date | Feb 5, 2015 |
| Publication date | Jul 26, 2016 |
| Grant date | Jul 26, 2016 |
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A load request is received to retrieve a piece of data from a location in memory and the load request follows one or more store requests in a set of instructions to store a piece of data in the location in memory. One or more possible locations in a cache for a piece of data corresponding to the location in memory is determined. Each possible location of the one or more possible locations in the cache is determined. It is then determined if at least one location of the one or more possible locations contains data to be stored in the location in memory. Data in one location of the at least one location is loaded, the data in the one location is from a store request of the one or more store requests and the store request is closest in the set of instructions to the load request.
Opening claim text (preview).
What is claimed is: 1. A method for executing a load with store forwarding data, the method comprising the steps of: receiving a load request, wherein the load request is a request to retrieve a piece of data from a location in memory, and wherein the load request follows one or more store requests in a set of instructions to store a piece of data in the location in memory, and wherein memory is one or more of the following: volatile computer readable storage media, non-volatile computer readable storage media, random access memory (RAM), cache, optical and magnetic drives, thumb drives, or smart cards; determining one or more possible locations in a cache for a piece of data corresponding to the location in memory, wherein the cache is an n-way associative cache, and wherein the cache contains a plurality of entries and wherein each entry includes the following: a logical address tag, a directory hit way tag, an instruction age/identifier tag, a byte validity indicator, and store data; utilizing a table, wherein the table includes a list of all store requests, processed but not retired, in the set of store instructions to store a piece of data in the location in memory; determining whether the one or more possible locations contain data corresponding to each store request of the store requests in the table; responsive to determining the one or more possible locations does not contain data corresponding to each store request of the store requests in the table, rejecting the loaded data; responsive to determining the one or more possible locations in the cache, reading each possible location of the one or more possible locations in the cache; determining if at least one location of the one or more possible locations contains data to be stored in the location in memory; responsive to determining that the at least one location of the one or more possible locations contains data to be stored in the location in memory, loading data in one location of the at least one location, wherein the data in the one location is from a store request of the one or more store requests, and wherein the store request is closest in the set of instructions to the load request; determining that the loaded data contained a portion of total data requested by the load request; and responsive to determining the loaded data contained a portion of total data requested by the load request, loading, from memory, a remaining portion of the total data requested by the load request.
using pseudo-associative means, e.g. set-associative or hashing · CPC title
Details of cache memory · CPC title
Instruction code · CPC title
in combination with broadcast means (e.g. for invalidation or updating) · CPC title
Cache access modes · CPC title
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