Microprocessor for gating a load operation based on entries of a prediction table

Patent metadata

Field	Value
Publication number	US-10198265-B2
Application number	US-201314063173-A
Country	US
Kind code	B2
Filing date	Oct 25, 2013
Priority date	Mar 15, 2013
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

A method for gating a load operation based on entries of a prediction table is presented. The method comprises performing a look-up for the load operation in a prediction table to find a matching entry, wherein the matching entry corresponds to a prediction regarding a behavior of the load operation, and wherein the matching entry comprises: (a) a tag field operable to identify the matching entry; (b) a distance field operable to indicate a distance of the load operation to a prior aliasing store instruction; and (c) a confidence field operable to indicate a prediction strength generated by the prediction table. The method further comprises determining if the matching entry provides a valid prediction and, if valid, retrieving a location for the prior aliasing store instruction using the distance field. The method finally comprises performing a gating operation on the load operation.

First claim

What is claimed is:

1. A set of one or more non-transitory computer readable storage media storing instructions, which when executed by a microprocessor, causes said microprocessor to perform operations for gating a load operation based on entries of a memory resident data structure, said operations comprising:
performing a look-up for said load operation in said memory resident data structure to find a matching entry, wherein said memory resident data structure is a prediction table, wherein said matching entry within said prediction table corresponds to a prediction regarding a dependence of said load operation on a prior aliasing store instruction, and wherein said matching entry comprises:
a tag field operable to identify said matching entry in said prediction table,
a distance field operable to indicate a distance of said load operation to said prior aliasing store instruction, and
a confidence field operable to indicate a prediction strength, wherein said prediction strength influences a gating of said load operation;

determining if said matching entry provides a valid prediction by comparing a value of said confidence field with a threshold value;
responsive to a determination of a valid prediction, retrieving a location for said prior aliasing store instruction using a value of said distance field; and
performing a gating operation on said load operation, wherein said gating operation prevents dispatching of said load operation; and
updating said matching entry after said load operation has executed by providing feedback from a load store queue responsive to a determination at said load store queue that said matching entry provided a valid prediction and a determination that there is no forwarding to said load operation from any store, wherein said determination at said load store queue that said matching entry provided a valid prediction is made based on a hit indicator set at a scheduler and passed along a microprocessor pipeline from said scheduler to said load store queue, wherein said feedback includes a distance parameter that is set to zero to indicate that there is no forwarding to said load operation from any store to thereby cause said prediction strength indicated in said confidence field to be decreased, and wherein said distance parameter is otherwise used to represent a distance between said load operation and a store operation when there is forwarding from said store operation to said load operation.

2. The set of one or more non-transitory computer readable storage media of claim 1 , wherein said performing a look-up, said determining if said matching entry provides a valid prediction by comparing a value of said confidence field with a threshold value, said retrieving, and said performing a gating operation are executed within said scheduler of said microprocessor pipeline.

3. The set of one or more non-transitory computer readable storage media of claim 2 , wherein said gating operation prevents dispatching of said load operation until said prior aliasing store instruction has executed.

4. The set of one or more non-transitory computer readable storage media of claim 2 , wherein
said feedback is provided from said load store queue in a memory stage of said microprocessor pipeline.

5. The set of one or more non-transitory computer readable storage media of claim 2 , wherein said operations further comprise:
incrementing the value of said confidence field in said prediction table in response to a determination that said tag field and said distance field of said matching entry match tag and distance information of said load operation.

6. The set of one or more non-transitory computer readable storage media of claim 2 , wherein said operations further comprise:
decrementing the value of said confidence field in said prediction table in response to a determination that said tag field and said distance field of said matching entry do not match tag and distance information of said load operation.

7. The set of one or more non-transitory computer readable storage media of claim 1 , wherein a value of said tag field is generated using a Program Counter (PC) value of said load operation.

8. The set of one or more non-transitory computer readable storage media of claim 1 , wherein said value of said distance field is calculated by subtracting a Reorder Buffer Identification of said prior aliasing store instruction from a Reorder Buffer Identification of said load operation.

9. A set of one or more non-transitory computer readable storage media storing instructions, which when executed by a microprocessor, causes said microprocessor to perform operations for gating a load operation, said operations comprising:
performing a look-up for said load operation in a first memory resident data structure to find a first matching entry, wherein said first memory resident data structure is a first prediction table residing in a scheduler of a microprocessor pipeline, wherein said first matching entry within said first prediction table corresponds to a prediction regarding a dependence of said load operation on a prior aliasing store instruction, and wherein said first matching entry comprises:
a tag field operable to identify said first matching entry in said first prediction table,
a distance field operable to indicate a distance of said load operation to said prior aliasing store instruction, and
a confidence field operable to indicate a prediction strength, wherein said prediction strength influences a gating of said load operation;

determining if said first matching entry provides a valid prediction by comparing a value of said confidence field with a threshold value;
responsive to a determination of a valid prediction, retrieving a location for said prior aliasing store instruction using a value of said distance field;
performing a first gating operation on said load operation, wherein said first gating operation prevents dispatching of said load operation until said prior aliasing store instruction has executed; and
updating said first matching entry after said load operation has executed by providing feedback from a load store queue responsive to a determination at said load store queue that said first matching entry provided a valid prediction and a determination that there is no forwarding to said load operation from any store, wherein said determination at said load store queue that said first matching entry provided a valid prediction is made based on a hit indicator set at said scheduler and passed along said microprocessor pipeline from said scheduler to said load store queue, wherein said feedback includes a distance parameter that is set to zero to indicate that there is no forwarding to said load operation from any store to thereby cause said prediction strength indicated in said confidence field to be decreased, and wherein said distance parameter is otherwise used to represent a distance between said load operation and a store operation when there is forwarding from said store operation to said load operation.

10. The set of one or more non-transitory computer readable storage media of claim 9 , wherein
said feedback is provided from said load store queue in a memory stage of said microprocessor pipeline.

11. The set of one or more non-transitory computer readable storage media of claim 10 , wherein said operations further comprise:
incrementing the value of said confidence field in said first prediction table in response to a determination that said tag field and said distance field of said first matching entry match tag and distance information of said load operation.

12. The set of one or more non-transitory computer readable storage me

Assignees

• Intel Corp

Inventors

• Zeng Hui

Classifications

• G06F9/3834 Primary

  Maintaining memory consistency · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/3826

  Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage · CPC title