Semiconductor memory device including a control circuit and at least two memory cell arrays

Patent metadata

Field	Value
Publication number	US-9396775-B2
Application number	US-201414475493-A
Country	US
Kind code	B2
Filing date	Sep 2, 2014
Priority date	Mar 14, 2014
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A memory device includes first and second memory cell arrays, and a control circuit configured to output first information indicating whether the first memory cell array is in a ready state in which the control circuit is ready to receive a command to access the first memory cell array or a busy state in which the control circuit is not ready to receive the command to access the first memory cell array, and second information indicating whether the second memory cell array is in a ready state in which the control circuit is ready to receive a command to access the second memory cell array or a busy state in which the control circuit is not ready to receive the command to access the second memory cell array.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
first and second memory cell arrays;
a control circuit configured to output first information indicating whether the first memory cell array is in a ready state in which the control circuit is ready to receive a command to access the first memory cell array or a busy state in which the control circuit is not ready to receive the command to access the first memory cell array, and second information indicating whether the second memory cell array is in a ready state in which the control circuit is ready to receive a command to access the second memory cell array or a busy state in which the control circuit is not ready to receive the command to access the second memory cell array, wherein the control circuit includes a first pad through which the first information is output and a second pad through which the second information is output; and
first and second caches that respectively hold data transferred from the first and second memory cell arrays, wherein
when the first information indicates that the first memory cell array is in the ready state, the first cache is accessible from outside the device,
when the second information indicates that the second memory cell array is in the ready state, the second cache is accessible from outside the device, and
when the control circuit receives a first command to access the first memory cell array and a second command to access the second memory cell array after receiving the first command, the control circuit is configured to perform a process instructed by the first command and then perform a process instructed by the second command within a time period that is shorter than two times a time period for completing the process instructed by the first command.

2. The device according to claim 1 , wherein
if the first command and the second command accesses a same page in the first and second memory cell arrays, the same page in the first and second memory cell arrays are accessed at the same time.

3. The device according to claim 1 , wherein, while the control circuit is executing the process instructed by the first command, the control circuit suspends the process instructed by the second command so that the same page in the first and second memory cell arrays can be accessed at the same time.

4. The device according to claim 1 , wherein
if the first command and the second command accesses a different page in the first and second memory cell arrays, a page in the first memory cell array is accessed and thereafter a page in the second memory cell array is accessed.

5. The device according to claim 1 , wherein the first information and the second information are output as a series of status bits.

6. A semiconductor memory device, comprising:
first and second memory cell arrays; and
a control circuit configured to output first information indicating whether the control circuit is in a first ready state or a first busy state and second information indicating whether the control circuit is in a second ready state or a second busy state, wherein
the control circuit is ready to receive a first command to access the first memory cell array when in the first ready state and is not ready to receive the first command when in the first busy state,
the control circuit is ready to receive a second command to access the second memory cell array when in the second ready state and not ready to receive the second command when in the second busy state,
the control circuit is configured to output the first information indicating the control circuit is in the first busy state after the semiconductor memory device receives the first command and to perform a first core operation in the first memory cell array while in the first busy state, and
the control circuit is configured to be able to receive the second command while in the first busy state, wait until the first core operation is finished, and then perform a second core operation in the second memory cell array.

7. The device according to claim 1 , wherein the control circuit is configured to perform the second core operation once the control circuit outputs the first information indicating the control circuit is in the first ready state after the first core operation is finished.

8. The device according to claim 1 , wherein the control circuit is configured to output the second information indicating the control circuit is in the second busy state after receiving the second command.

9. The device according to claim 1 , wherein the control circuit is configured to perform a first pre-fetch operation and a first dummy end operation while in the first busy state.

10. The device according to claim 9 , wherein the control circuit is configured to perform a second address transfer operation after performing the first dummy end operation and before performing the second core operation.

11. The device according to claim 6 , wherein the first and second core operations are read operations.

12. The device according to claim 6 , wherein the first information and the second information are output as a series of status bits.

13. The device according to claim 6 , wherein the control circuit includes a first pad through which the first information is output and a second pad through which the second information is output.

14. The device according to claim 6 , wherein the control circuit is configured to perform an operation instructed by the first command and then perform an operation instructed by the second command within a time period that is shorter than two times a time period for completing the operation instructed by the first command.

15. The device according to claim 6 , wherein the control circuit includes a first register for storing an address specified in the first command and a second register for storing an address specified in the second command.

Assignees

• Toshiba Kk

Inventors

• Shirakawa Masanobu
• Hara Tokumasa

Classifications

• G11C7/1063 Primary

  Control signal output circuits, e.g. status or busy flags, feedback command signals · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F2212/452

  Instruction code · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G11C7/24

  Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells · CPC title