Storage device that restores data lost during a subsequent data write

Patent metadata

Field	Value
Publication number	US-10248560-B2
Application number	US-201715714776-A
Country	US
Kind code	B2
Filing date	Sep 25, 2017
Priority date	Sep 26, 2016
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A storage device that can be connected to a host device includes a plurality of nonvolatile memories. Each nonvolatile memory includes first memory cells connected to a first word line and second memory cells connected to a second word line. The second word line is adjacent to the first word line. A controller in the storage device is configured to maintain parity data in a memory area of the host device for the data that has been written to the first memory cells, and, upon detecting a failure in the writing of data to the second memory cells, restore the data written to the first memory cells using the parity data from the memory area of the host device.

First claim

What is claimed is:

1. A storage device connectable to a host device, the storage device comprising:
a plurality of nonvolatile memories each including first memory cells connected to a first word line and second memory cells connected to a second word line that is adjacent to the first word line; and
a controller configured to:
maintain parity data in a memory area of the host device for data that has been written to the first memory cells,
write data to the second memory cells, and
upon detecting a failure in the writing of data to the second memory cells, restore, using the parity data from the memory area of the host device, the data previously written to the first memory cells.

2. The storage device according to claim 1 , wherein the nonvolatile memories in the plurality of nonvolatile memories are flash memory devices.

3. The storage device according to claim 1 , wherein the controller is further configured to write the data restored using the parity data to memory cells connected to a third word line.

4. The storage device according to claim 1 , wherein the controller is further configured to generate the parity data for data written to the first memory cells by performing an exclusive OR operation on the data written in the first memory cells.

5. The storage device according to claim 1 , further comprising:
a volatile memory in the controller, wherein
the controller also maintains parity data in the volatile memory.

6. A storage device connectable to a host device, the storage device comprising:
a plurality of nonvolatile memories, each nonvolatile memory in the plurality of nonvolatile memories including a first memory cell array and a second memory cell array, each memory cell array in the nonvolatile memories including first memory cells connected to a first word line and second memory cells connected to a second word line that is adjacent to the first word line; and
a memory controller including a host interface control unit for communicating with the host device, a buffer for storing data to be written to or read from the plurality of nonvolatile memories, wherein the memory controller is configured to:
maintain parity data in a memory area of the host device for data that has been written to first memory cells,
write data to second memory cells, and
upon detecting a failure in the writing of data to the second memory cells, restore, using the parity data from the memory area of the host device, the data previously written to the first memory cells of a designated nonvolatile memory in the plurality of nonvolatile memories.

7. The storage device according to claim 6 , wherein the memory controller uses data previously written to the first memory cells of other than the designated nonvolatile memory.

8. The storage device according to claim 6 , wherein the memory controller is further configured to write the data that was restored using the parity data to memory cells in the designated nonvolatile memory that are connected to a third word line that is different from the first and second word lines.

9. The storage device according to claim 6 , wherein the memory controller is further configured to generate the parity data by performing an exclusive OR (XOR) operation on the data.

10. The storage device according to claim 6 , wherein the memory controller is further configured to generate the parity data by performing a first exclusive OR (XOR) operation on the data written in the first memory cells of the first memory cell arrays of the plurality of nonvolatile memories, and a second exclusive OR (XOR) operation on data written to the first memory cells of the second memory cell arrays of the plurality of nonvolatile memories.

11. The storage device according to claim 10 , wherein the parity data is generated by performing a third exclusive OR (XOR) operation on results from the first and second exclusive OR (XOR) operations.

12. The storage device according to claim 6 , further comprising:
a volatile memory in the memory controller, wherein
the memory controller also maintains parity data in the volatile memory.

13. The storage device according to claim 6 , wherein the memory controller is further configured to:
generate second parity data for data written to the second memory cells in the second memory cell arrays of the plurality of nonvolatile memories,
read data from the second memory cells in the second memory cell array of the designated nonvolatile memory, and
restore, using the second parity information, data previously written to the second memory cells in the second memory cell array of the designated nonvolatile memory upon detecting a failure in the reading of data from the second memory cells in the second memory cell array of the designated nonvolatile memory.

14. The storage device according to claim 13 , wherein the memory controller uses data written to the second memory cells of other than the designated nonvolatile memory.

15. The storage device according to claim 13 , wherein the memory controller is further configured to write data restored using the second parity data to memory cells in the designated nonvolatile memory that are connected to a third word line that is different from the first and second word lines.

16. The storage device according to claim 13 , wherein the memory controller is further configured to generate the second parity data by performing an exclusive OR operation on the data written in the second memory cells of the second memory cell arrays of the plurality of nonvolatile memories.

17. The storage device according to claim 13 , wherein the controller maintains the second parity data in the memory area of the host device.

18. A method for operating a storage device connected to a host device, the storage device including a plurality of nonvolatile memories each of which includes first memory cells connected to a first word line and second memory cells connected to a second word line that is adjacent to the first word line, the method comprising:
generating parity data for data written to first memory cells, the parity data being error correction information permitting restoration of the data;
maintaining the parity data in a memory area of the host device;
attempting to write data to the second memory cells; and
upon detecting a failure in the writing of data writing to the second memory cells, using the parity data from the memory area of the host device to restore the data previously written to the first memory cells.

19. The method according to claim 18 , further comprising:
writing the restored data to memory cells connected to a third word line that is different from the first and second word lines.

Assignees

• Toshiba Memory Corp

Inventors

• Ohno Katsuya
• Watanabe Konosuke
• Yasufuku Kenta

Classifications

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H03M13/2942

  wherein a block of parity bits is computed only from combined information bits or only from parity bits, e.g. a second block of parity bits is computed from a first block of parity bits obtained by systematic encoding of a block of information bits, or a block of parity bits is obtained by an XOR combination of sub-blocks of information bits · CPC title

• G06F11/1072

  in multilevel memories · CPC title