Memory systems and methods for improved power management

Patent metadata

Field	Value
Publication number	US-11309017-B2
Application number	US-202017100850-A
Country	US
Kind code	B2
Filing date	Nov 21, 2020
Priority date	Nov 20, 2014
Publication date	Apr 19, 2022
Grant date	Apr 19, 2022

Abstract

A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

First claim

What is claimed is:

1. A memory module comprising:
memory devices each having a data interface, an address interface, an enable interface, and a chip-select interface; and
a command-buffer component coupled to the address interfaces, enable interfaces, and chip-select interfaces of the memory devices, the command-buffer component to receive memory commands, memory addresses associated with the memory commands, and encoded chip-select information associated with the memory commands, the command-buffer component decoding the chip-select information, responsively issuing an enable signal to a subset of the enable interfaces to enable a corresponding subset of the memory devices, and issuing chip-select signals to ones of the enabled subset of the memory devices.

2. The memory module of claim 1 , wherein the command-buffer component divides the memory devices into sub-ranks of memory devices, the number of memory devices in each of the sub-ranks of the memory devices a function of a configuration value.

3. The memory module of claim 2 , wherein the memory module is one of multiple memory modules in a memory system, and wherein the configuration value indicates the number of the memory modules in the memory system.

4. The memory module of claim 2 , wherein the memory module is one of multiple memory modules in a memory system, and each of the memory modules enabling one of the sub-ranks of the memory devices.

5. The memory module of claim 1 , wherein the command-buffer component decodes the chip-select information to issue the enable signals and second chip-select information to issue the chip-select signals to ones of the enabled subset of the memory devices.

6. The memory module of claim 5 , the command-buffer component including a register to store the decoded chip-select information pending receipt of the second chip-select information.

7. The memory module of claim 1 , further comprising a data-buffer component coupled to at least one of the memory devices, the command-buffer component to issue a data-buffer enable signal to the data-buffer component responsive to the decoded chip-select information.

8. A method for providing access to a rank of memory devices on at least one memory module, the rank including a first sub-rank of memory devices and a second sub-rank of memory devices, the method comprising:
receiving an enable command at the at least one memory module, the enable command accompanying chip-select information;
powering the memory devices in the first and second sub-ranks of the memory devices responsive to the chip-select information; and
asserting chip-select signals to the powered memory devices in the first and second sub-ranks of the memory devices responsive to the chip-select information.

9. The method of claim 8 , wherein the rank of memory devices are a set of memory devices accessed simultaneously, and each of the first and second sub-ranks is a module-specific fraction of the rank.

10. The method of claim 8 , further comprising:
storing the chip-select information accompanying the enable command;
receiving a second command with the chip-select information;
powering the memory devices in the first and second sub-ranks of the memory devices responsive to the stored chip-select information; and
asserting the chip-select signals responsive to the second command.

11. The method of claim 8 , wherein powering the memory devices comprises commanding the memory devices to exit a low-power mode.

12. The method of claim 8 , further comprising:
receiving an activate command at the at least one memory module; and
activating the first and second sub-ranks of the memory devices responsive to the activate command.

13. The method of claim 8 , the memory module further including data buffers to communicate data with the memory devices, the method further comprising powering a subset of the data buffers responsive to the chip-select information.

14. A memory module comprising:
a number of memory devices each having a memory-device enable terminal;
a command port to receive commands from a controller component external to the memory module; and
a decoder communicatively coupled to the command port and the memory-device enable terminals, the decoder to:
receive a configuration value from the controller component specifying a fraction of the number of the memory devices;
receive, as one of the commands, an enable command accompanying chip-select information;
decode the chip-select information responsive to the configuration value specifying the fraction of the number of the memory devices, the decoding specifying a subset of the memory devices, the subset of the memory devices of the fraction of the number of the memory devices; and
power the specified subset of the memory devices responsive to the decoded chip-select information.

15. The memory module of claim 14 , wherein the decoder is instantiated on a command-buffer component on the memory module.

16. The memory module of claim 15 , further comprising data-buffer components coupled to the memory devices to communicate data between the memory devices and the controller component.

17. The memory module of claim 16 , wherein the decoder directs the data-buffer components responsive to the configuration value.

18. The memory module of claim 17 , the decoder including a register to store the configuration value.

19. The memory module of claim 17 , the decoder including a register to store a value specifying the subset of the memory devices.

20. The memory module of claim 17 , the decoder including a register to store the decoded chip-select information.

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Harris James E

Classifications

• G11C11/4093 Primary

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title