Methods and apparatuses for controlling timing paths and latency based on a loop delay

Patent metadata

Field	Value
Publication number	US-9508417-B2
Application number	US-201414185194-A
Country	US
Kind code	B2
Filing date	Feb 20, 2014
Priority date	Feb 20, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

Apparatuses and methods for controlling timing circuit locking and/or latency during a change in clock frequency (e.g. gear down mode) are described herein. An example apparatus may include a timing circuit. The timing circuit may be configured to provide a clock signal to the forward path, adjust a rate of the clock signal responsive to receipt of a command to adjust the rate of the clock signal, select a feedback clock signal responsive to a loop delay of the timing circuit, and provide a control signal to an adjustable delay circuit of the forward path circuit. Another example apparatus may include a forward path configured to delay a signal based at least in part on a loop delay and a latency value, and a latency control circuit configured to provide an adjusted latency value as the latency value responsive to receipt of a command, wherein the forward path is configured to operate at least in part at an adjusted clock rate responsive to receipt of the command.

First claim

What is claimed is:

1. An apparatus comprising:
a forward path circuit configured to delay a signal; and
a timing circuit configured to:
provide a clock signal to the forward path;
adjust a rate of the clock signal responsive to receipt of a command to adjust the rate of the clock signal;
select a first feedback clock signal responsive to a loop delay of the timing circuit comprising an even number of clock cycles;
select a second feedback clock signal responsive to the loop delay of the timing circuit comprising an odd number of clock cycles; and
provide a control signal to an adjustable delay circuit of the forward path circuit.

2. The apparatus of claim 1 , wherein the timing circuit is configured to provide the first feedback clock signal that is in-phase with an input clock signal responsive to the loop delay comprising an even number of clock cycles.

3. The apparatus of claim 1 , wherein the timing circuit is configured to provide the second feedback clock signal that is out of phase with an input clock signal responsive to the loop delay comprising an odd number of clock cycles.

4. The apparatus of claim 3 , wherein the timing circuit comprises a phase splitter configured to provide the out of phase second feedback clock signal.

5. The apparatus of claim 1 , wherein timing circuit comprises a phase detector configured to provide the loop delay.

6. The apparatus of claim 1 , wherein the timing circuit comprises a delay locked loop.

7. An apparatus comprising:
a forward path circuit configured to delay a signal; and
a timing circuit configured to:
provide a clock signal to the forward path;
adjust a rate of the clock signal responsive to receipt of a command to adjust the rate of the clock signal;
select a feedback clock signal responsive to a loop delay of the timing circuit; and
provide a control signal to an adjustable delay circuit of the forward path circuit, wherein the timing circuit being configured to reduce a rate of the clock signal comprises the timing circuit being configured to reduce the rate of the clock signal by half.

8. An apparatus comprising:
a forward path circuit configured to delay a signal; and
a timing circuit configured to:
provide a clock signal to the forward path;
adjust a rate of the clock signal responsive to receipt of a command to adjust the rate of the clock signal;
select a feedback clock signal responsive to a loop delay of the timing circuit;
provide a control signal to an adjustable delay circuit of the forward path circuit; and

a latency control circuit coupled to a shift circuit and configured to provide an adjusted latency value responsive to receipt of the command.

9. An apparatus comprising:
a forward path configured to delay a signal based at least a on a loop delay and a latency value; and
a latency control circuit configured to provide an adjusted latency value as the latency value and an adjusted loop delay as the loop delay responsive to receipt of a command, wherein the forward path is configured to operate at least in part at an adjusted clock rate responsive to receipt of the command.

10. The apparatus of claim 9 , further comprising a timing circuit configured to provide a clock signal to the forward path.

11. The apparatus of claim 10 , wherein the timing circuit is further configured to reduce a rate of the clock signal responsive to receipt of the command.

12. The apparatus of claim 11 , wherein the timing circuit is configured to provide the adjusted latency value and the adjusted loop delay to a shift circuit of the forward path.

13. The apparatus of claim 10 , wherein the timing circuit is configured to adjust the delay of the forward path signal based on the adjusted clock rate of the forward path operation.

14. The apparatus of claim 9 , wherein the adjusted loop delay comprises the loop delay divided by two if the loop delay is an even number of clock cycles.

15. The apparatus of claim 9 , wherein the adjusted loop delay comprises the loop delay divided by two and rounded up to the next integer if the loop delay is an odd number of clock cycles.

16. The apparatus of claim 15 , further comprising a signal distribution network coupled to the forward path, wherein the signal distribution network is configured to add an additional delay to a signal propagating through the network if the loop delay is an odd number of clock cycles.

17. A method comprising:
adjusting a clock rate of a timing circuit;
determining a feedback clock signal used by the timing circuit based on whether a loop delay of the timing circuit comprises an even number of clock cycles or an odd number of clock cycles; and
adjusting a delay of a shift circuit based at least in part on an adjusted loop delay.

18. The method of claim 17 , further comprising:
adjusting the loop delay responsive to receipt of a command to adjust the clock rate to provide the adjusted loop delay.

19. A method comprising:
adjusting a clock rate of a timing circuit;
determining a feedback clock signal used by the timing circuit based on a loop delay of the timing circuit; and
adjusting a delay of a shift circuit based at least in part on an adjusted loop delay; and
adjusting the loop delay responsive to receipt of a command to adjust the clock rate to provide the adjusted loop delay, wherein adjusting the loop delay comprises dividing the loop delay by two and rounding up to a next integer if the loop delay comprises an odd number of dock cycles.

20. A method comprising;
adjusting a clock rate of a timing circuit;
determining a feedback clock signal used by the timing circuit based on a loop delay of the timing circuit; and
adjusting a delay of a shift circuit based at least in part on an adjusted loop delay, wherein determining a feedback clock signal used by the timing circuit based on a loop delay comprises:
selecting an in-phase clock signal for the feedback signal based on the loop delay comprising an even number of clock cycles, wherein the in-phase clock signal is in-phase with an input clock signal; and
selecting an out of phase clock signal for the feedback signal based on the loop delay comprising an odd number of clock cycles, wherein the out of phase clock signal is out of phase with the input clock signal.

21. A method comprising:
adjusting a clock rate of a timing circuit;
determining a feedback clock signal used by the timing circuit based on a loop delay of the timing circuit; and
adjusting a delay of a shift circuit based at least in tart on adjusted loop delay, wherein adjusting a clock rate of a timing circuit comprises reducing the clock rate by half.

22. A method comprising:
adjusting a clock rate of a timing circuit;
determining a feedback clock signal used by the timing circuit based on a loop delay of the timing circuit;
adjusting a delay of a shift circuit based at least in part an adjusted loop delay and:
when the loop delay comprises an odd number of clock cycles, adding additional delay to a signal propagating through a signal distribution network.

Assignees

• Micron Technology Inc

Inventors

• Kwak Jongtae

Classifications

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C11/4076 Primary

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C2207/2272

  Latency related aspects · CPC title