Data transmission using delayed timing signals

Patent metadata

Field	Value
Publication number	US-9843315-B2
Application number	US-201214351955-A
Country	US
Kind code	B2
Filing date	Oct 26, 2012
Priority date	Nov 1, 2011
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first delay circuit to delay a first timing signal by an internal delay to generate an internal timing signal;
a first interface circuit to communicate data to an external device in response to the internal timing signal;
a second interface circuit to transmit an external timing signal for capturing the data in the external device; and
a second delay circuit to delay the first timing signal by a second internal delay to generate a second internal timing signal, wherein the external timing signal is generated based on the second internal timing signal during a normal mode, and wherein the external timing signal is generated using a circuit path that bypasses the second delay circuit during a calibration mode.

2. The integrated circuit of claim 1 , further comprising:
a circuit to receive a phase comparison signal from the external device, wherein the first delay circuit sets the internal delay based on the phase comparison signal.

3. The integrated circuit of claim 1 , further comprising:
a multiplexer circuit configurable to cause the first interface circuit to communicate the data in response to the first timing signal or the internal timing signal.

4. The integrated circuit of claim 1 , wherein the external timing signal is generated based on the first timing signal during the calibration mode.

5. The integrated circuit of claim 1 , wherein the internal delay is adjusted to cause the first interface circuit to communicate the data with an approximate quadrature-phase relationship with the external timing signal.

6. The integrated circuit of claim 1 , wherein the external device comprises a memory circuit, and wherein the first interface circuit communicates the data during a write operation to the memory circuit.

7. A method comprising:
delaying a first timing signal by an internal delay using a first delay circuit to generate an internal timing signal;
communicating data to an external device using a first interface circuit in response to the internal timing signal;
transmitting an external timing signal for capturing the data in the external device using a second interface circuit, wherein an external delay is added to the external timing signal in the external device to generate a delayed external timing signal;
setting the internal delay of the first delay circuit based on a comparison in the external device between the delayed external timing signal and a signal transmitted by the first interface circuit; and
delaying the first timing signal by a second internal delay using a second delay circuit to generate a second internal timing signal, wherein the external timing signal is generated based on the second internal timing signal during a normal mode, and wherein the external timing signal is generated using a circuit path that bypasses the second delay circuit during a calibration mode.

8. The method of claim 7 further comprising:
adjusting the internal delay to substantially match the external delay.

9. The method of claim 7 further comprising:
generating the external timing signal based on the first timing signal during the calibration mode.

10. The method of claim 7 , wherein the external delay is caused by a buffer circuit to drive the delayed external timing signal to a plurality of data capture circuits in the external device.

11. The method of claim 7 , wherein communicating data to an external device using a first interface circuit in response to the internal timing signal comprises communicating the data during a write operation to a memory circuit in the external device.

12. The method of claim 7 , further comprising:
selectively causing the first interface circuit to communicate the data in response to the first timing signal or the internal timing signal.

13. The method of claim 7 , wherein the internal delay is adjustable, and the external delay is non-adjustable.

14. The method of claim 7 , further comprising:
adjusting the internal delay to cause the first interface circuit to communicate the data with an approximate quadrature-phase relationship with the external timing signal.

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Tsern Ely
• Leibowitz Brian
• Zerbe Jared

Classifications

• G11C7/1066

  Output synchronization · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C7/1093

  Input synchronization · CPC title

• G06F13/00

  Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor  G06F9/46}; multiprocessor systems  G06F15/16 ) · CPC title