Semiconductor memory device with a delay locked loop circuit and a method for controlling an operation thereof

Patent metadata

Field	Value
Publication number	US-9443565-B2
Application number	US-201414219181-A
Country	US
Kind code	B2
Filing date	Mar 19, 2014
Priority date	Mar 29, 2013
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

An operation control method of a semiconductor memory device includes executing a Delay Locked Loop (DLL) locking in response to a DLL reset signal and measuring a loop delay of a DLL. The operation control method further includes storing measured loop delay information and DLL locking information; and performing a delay control of a command path using the stored loop delay information and DLL locking information independent of the DLL, during a latency control operation.

First claim

What is claimed is:

1. An operation control method of a semiconductor memory device, comprising:
executing a Delay Locked Loop (DLL) locking in response to a DLL reset signal;
measuring a loop delay of a DLL;
storing measured loop delay information and DLL locking information; and
performing a delay control of a command path using the stored loop delay information and DLL locking information during a latency control operation, wherein the delay control is performed while the DLL is inactive,
wherein the loop delay information is used to determine an additive delay of an additive delay line included in the command path,
wherein the loop delay is measured by counting a feedback clock applied to a phase detector of the DLL within an interval.

2. The operation control method of claim 1 , wherein the DLL comprises a clock path, wherein the command path and the clock path are driven independently from each other.

3. The operation control method of claim 1 , wherein the DLL locking information is used to determine a DLL delay of a delay line replica that is connected to an output of the additive delay line and wherein the delay line replica has the same delay as that of a delay line of the DLL.

4. The operation control method of claim 1 , wherein a latency value applied through the command path is used to determine the additive delay.

5. The operation control method of claim 1 , wherein a number of rising edges of the feedback clock are counted.

6. A semiconductor memory device, comprising:
a Delay Locked Loop (DLL) configured to execute a DLL locking at a DLL reset;
a DLL control part configured to control the DLL and store DLL locking information at the DLL locking;
a loop delay measure circuit configured to measure and store a loop delay of the DLL; and
a command path unit including an additive delay line configured to determine an additive delay in response to the stored loop delay, and a delay line replica having the same delay as that of a delay line of the DLL and configured to determine a DLL line delay in response to the DLL locking information,
wherein during a latency control operation, a delay control of the command path unit is performed using the stored loop delay and DLL locking information,
wherein the delay control is performed while the DLL is inactive,
wherein the DLL comprises:
a DLL delay line configured to delay an input clock according to a delay selection signal;
a data output buffer replica having the same delay as a delay of a data output buffer and configured to receive an output clock of the DLL delay line;
a clock buffer replica having the same delay as a delay of a clock buffer and configured to receive an output buffer clock from the data output buffer replica; and
a phase detector configured to generate a phase error detection signal by comparing the input clock with a feedback clock from the clock buffer replica.

7. The semiconductor memory device of claim 6 , wherein the DLL control part controls the DLL in response to the phase error detection signal and latches the delay selection signal as the DLL locking information at the DLL locking.

8. The semiconductor memory device of claim 6 , wherein the loop delay measure circuit measures the loop delay of the DLL by counting a result obtained by comparing the feedback clock and the input clock within an interval.

9. The semiconductor memory device of claim 6 , wherein the loop delay measure circuit comprises:
a counting circuit configured to count a result obtained by comparing the feedback clock and the input clock within an interval;
a decoder configured to decode the count result; and
an adder configured to generate the additive delay information using a decoding output value of the decoder and a latency value.

10. The semiconductor memory device of claim 9 , wherein the command path unit further comprises:
a command buffer; and
a command decoder connected between the command buffer and the additive delay line.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Hangi

Classifications

• G11C7/02 Primary

  with means for avoiding parasitic signals · CPC title

• G11C2207/2272

  Latency related aspects · CPC title

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C11/4072

  Circuits for initialization, powering up or down, clearing memory or presetting · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title