Integrated interposer solutions for 2D and 3D IC packaging

Patent metadata

Field	Value
Publication number	US-11302616-B2
Application number	US-201916288720-A
Country	US
Kind code	B2
Filing date	Feb 28, 2019
Priority date	Jun 4, 2014
Publication date	Apr 12, 2022
Grant date	Apr 12, 2022

Abstract

An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.

First claim

What is claimed is:

1. A method for making an integrated circuit (IC) package, the method comprising:
providing a first substrate having a back side surface and a top surface;
forming a cavity in the top surface of the first substrate, the cavity having a floor defining a front side surface;
forming electroconductive contacts on respective ones of the front and back side surfaces;
forming a plurality of electroconductive elements penetrating through the first substrate and interconnecting selected ones of the electroconductive contacts respectively disposed on the front and back side surfaces to each other;
disposing one or more dies within the cavity and electroconductively coupling each die to corresponding ones of the electroconductive contacts disposed on the front side surface, each die containing an IC;
injecting a dielectric material into the cavity to encapsulate the one or more dies;
after injecting a dielectric material into the cavity to encapsulate the one or more dies, thinning (i) a top surface of the dielectric material, (ii) the top surface of the first substrate, and (iii) a top surface of each of the one or more dies until (i) the top surface of the dielectric material, (ii) the top surface of each of the one or more dies, and (iii) the top surface of the first substrate are substantially coplanar;
permanently sealingly attaching a bottom surface of a second substrate to the top surface of the first substrate, wherein a coefficient of thermal expansion (CTE) of the first substrate and a CTE of the second substrate are substantially matched; and
thinning the back side surface of the first substrate.

2. The method of claim 1 , further comprising:
coupling the back side surface of the first substrate to a wafer chuck,
wherein thinning (i) the top surface of the dielectric material, (ii) the top surface of the first substrate, and (iii) the top surface of each of the one or more dies comprises grinding (i) the top surface of the dielectric material, (ii) the top surface of each of the one or more dies, and (iii) the top surface of the first substrate until (i) the top surface of the dielectric material, (ii) the top surface of each of the one or more dies, and (iii) the top surface of the first substrate are substantially coplanar.

3. The method of claim 1 , further comprising:
coupling a top surface of the second substrate to a wafer chuck,
wherein thinning the back side surface of the first substrate comprises grinding the back side surface of the first substrate.

4. The method of claim 1 , wherein the forming of the electroconductive elements comprises reactive ion etching (RIE).

5. The method of claim 1 , wherein upon permanently sealingly attaching of the bottom surface of the second substrate to the top surface of the first substrate, the second substrate at least partially covers the cavity.

6. The method of claim 5 , wherein permanently sealingly attaching of the bottom surface of the second substrate to the top surface of the first substrate comprises anodic bonding of the bottom surface of the second substrate to the top surface of the first substrate outside the cavity.

7. The method of claim 5 , wherein permanently sealingly attaching of the bottom surface of the second substrate to the top surface of the first substrate comprises fusion bonding of the bottom surface of the second substrate to the top surface of the first substrate outside the cavity.

8. The method of claim 1 , wherein the dielectric material couples at least one die of the one or more dies with inner surfaces of the cavity.

9. The method of claim 1 , wherein thinning (i) the top surface of the dielectric material, (ii) the top surface of the first substrate, and (iii) the top surface of each of the one or more dies comprises etching (i) the top surface of the dielectric material, (ii) the top surface of the first substrate, and (iii) the top surface of each of the one or more dies.

10. The method of claim 1 , wherein thinning (i) the top surface of the dielectric material, (ii) the top surface of the first substrate, and (iii) the top surface of each of the one or more dies comprises mechanical polishing of (i) the top surface of the dielectric material, (ii) the top surface of the first substrate, and (iii) the top surface of each of the one or more dies.

11. The method of claim 1 , wherein thinning (i) the top surface of the dielectric material, (ii) the top surface of the first substrate, and (iii) the top surface of each of the one or more dies comprises chemical mechanical polishing of (i) the top surface of the dielectric material, (ii) the top surface of the first substrate, and (iii) the top surface of each of the one or more dies.

12. The method of claim 1 , wherein the plurality of electroconductive elements penetrating through the first substrate are formed after thinning the back side surface.

13. The method of claim 12 , wherein:
forming the plurality of electroconductive elements comprises forming through-holes in the back side surface of the first substrate; and
the method further comprises forming electroconductive material in the through-holes.

14. The method of claim 1 , wherein forming the plurality of electroconductive elements comprises:
providing the electroconductive elements before permanently sealingly attaching the bottom surface of the second substrate to the top surface of the first substrate; and
revealing the electroconductive elements by thinning process.

15. The method of claim 1 , wherein the electroconductive contacts formed on the back side surface are formed after permanently sealingly attaching the bottom surface of the second substrate to the top surface of the first substrate.

16. The method of claim 1 , wherein the electroconductive contacts formed on the back side surface are formed after thinning (i) the top surface of the dielectric material, (ii) the top surface of the first substrate, and (iii) the top surface of each of the one or more dies.

17. The method of claim 1 , wherein forming the cavity in the top surface of the first substrate comprises reactive ion etching (RIE).

Assignees

• Invensas Corp

Inventors

• Shen Hong
• Woychik Charles G
• Sitaram Arkalgud R
• Gao Guilian

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W76/18

  Insulating materials, e.g. resins, glasses or ceramics · CPC title

• H10W76/17

  characterised by their materials · CPC title