Low power ferroelectric based majority logic gate adder

Patent metadata

Field	Value
Publication number	US-11296708-B2
Application number	US-202017129830-A
Country	US
Kind code	B2
Filing date	Dec 21, 2020
Priority date	Dec 27, 2019
Publication date	Apr 5, 2022
Grant date	Apr 5, 2022

Abstract

An adder with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.

First claim

We claim:

1. An apparatus comprising:
a first 3-input majority gate to receive a first input, a second input, and a carry-in input;
a first inversion logic having an input coupled to the carry-in input, and an output;
a second 3-input majority gate to receive the first input, the second input, and the output of the first inversion logic;
a second inversion logic having an input coupled to an output of the first 3-input majority gate, and an output;
a non-inversion logic coupled to an output of the second 3-input majority gate; and
a third 3-input majority gate to receive the output of the second inversion logic, an output of the non-inversion logic, and the carry-in input, wherein each of the first, second, and third 3-input majority gates include a capacitor having non-linear polar material.

2. The apparatus of claim 1 comprising a third inversion logic having an input coupled to the output of the second inversion logic, and an output which is a carry-out.

3. The apparatus of claim 1 , wherein the non-inversion logic is a first non-inversion logic, wherein the apparatus comprising a second non-inversion logic coupled to an output of the third 3-input majority gate.

4. The apparatus of claim 1 , wherein the first 3-input majority gate comprises:
first, second, and third capacitors to receive the first input, the second input, and the carry-in input, respectively;
a non-linear polar capacitor to store a majority function output of the first input, the second input, and the carry-in input, wherein one terminal of the non-linear polar capacitor provides an output of the first 3-input majority gate;
a first transistor coupled to a first terminal of the non-linear polar capacitor, wherein the first transistor is controllable by a first clock;
a second transistor coupled to a second terminal of the non-linear polar capacitor, wherein the second transistor is controllable by a second clock; and
a third transistor coupled to the second terminal of the non-linear polar capacitor, wherein the third transistor is controllable by third clock.

5. The apparatus of claim 4 , wherein the first clock has a pulse width greater than a pulse width of the second clock and a pulse width of the third clock.

6. The apparatus of claim 4 , wherein the third clock is to de-assert prior to an assertion of the second clock.

7. The apparatus of claim 4 , wherein the first transistor is a first n-type transistor, wherein the second transistor is a second n-type transistor, and wherein the third transistor is a p-type transistor.

8. The apparatus of claim 4 , wherein the first transistor, the second transistor, and the third transistor are disabled in an evaluation phase, and enabled in a reset phase, wherein the reset phase is prior to the evaluation phase.

9. The apparatus of claim 4 , wherein the first and second transistors comprise CMOS transistors.

10. The apparatus of claim 4 , wherein the first, second, and third capacitors of the first 3-input majority gate comprises one of: a metal-insulator-metal (MIM) capacitor, a transistor gate capacitor, a hybrid of metal and transistor capacitor; or a capacitor comprising para-electric material.

11. The apparatus of claim 4 , wherein the non-linear polar capacitor is positioned in a backend of a die, while the first transistor and the second transistor are positioned in a frontend of the die.

12. The apparatus of claim 4 , wherein the non-linear polar capacitor includes one of: ferroelectric material, para-electric material, or non-linear dielectric.

13. The apparatus of claim 12 , wherein the ferroelectric material includes one of:
Bismuth ferrite (BFO), BFO with a doping material where in the doping material is one of Lanthanum, or elements from lanthanide series of periodic table;
Lead zirconium titanate (PZT), or PZT with a doping material, wherein the doping material is one of La or Nb;
relaxor ferro-electric which includes one of lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), Barium Titanium-Bismuth Zinc Niobium Tantalum (BT-BZNT), or Barium Titanium-Barium Strontium Titanium (BT-BST);
perovskite ferroelectrics which includes one of: BaTiO3, PbTiO3, KNbO3, or NaTaO3;
a hexagonal ferroelectric which includes one of: YMnO3 or LuFeO3;
hexagonal ferroelectrics of a type h-RMnO3, where R is a rare earth element including one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y);
Hafnium (Hf), Zirconium (Zr), Aluminum (Al), Silicon (Si), their oxides or their alloyed oxides;
Hafnium oxides as H1-x Ex Oy where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y;
Al(1-x)Sc(x)N, Ga(1-x)Sc(x)N, Al(1-x)Y(x)N or Al(1-x-y)Mg(x)Nb(y)N, y doped HfO2, where x includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y, wherein ‘x’ is a fraction;
Niobate type compounds LiNbO3, LiTaO3, Lithium iron Tantalum Oxy Fluoride, Barium Strontium Niobate, Sodium Barium Niobate, or Potassium strontium niobate; or
an improper ferroelectric which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 to 100.

14. The apparatus of claim 1 , wherein the first, second, and third inputs are analog signals, digital signals, or a combination of them.

15. The apparatus of claim 2 , wherein the first inversion logic, the second inversion logic, or the third inversion logic comprise one of: a buffer, a CMOS inverter, a NAND gate, or a NOR gate.

16. The apparatus of claim 1 comprises:
a first driver to generate the first input; and
a second driver to generate the second input.

17. An apparatus comprising:
a first 3-input majority gate to perform a first majority function on a first input, a second input and a carry-in input;
a second 3-input majority gate to perform a second majority function on the first input, the second input, and an inverse of the carry-in input; and
a third 3-input majority gate to perform a third majority function on an inverse output of the first 3-input majority gate, a buffered output of the second 3-input majority gate, and the carry-in input, wherein each of the first, second, and third 3-input majority gates include a capacitor having non-linear polar material.

18. The apparatus of claim 17 comprising a reset mechanism to reset the capacitor having the non-linear polar material, wherein the reset mechanism resets the capacitor having the non-linear polar material in a reset phase prior to an evaluation phase.

19. The apparatus of claim 17 comprises:
a first driver to generate the first input; and
a second driver to generate the second input.

20. The apparatus of claim 17 , wherein the first input or second input are an analog signal, a digital signal, or a combination of them.

21. The apparatus of claim 17 , wherein the non-linear polar material includes one of:
ferroelectric material, para-electric material, or non-linear dielectric.

22. The apparatus of claim 21 , wherein the ferroelectric material includes one of:
Bismuth ferrite (BFO), BFO with a doping material where in the doping material is one of Lanthanum, or elements from lanthanide series of periodic table;
Lead zirconium titanate (PZT), or PZT with a doping material, wherein the doping material is one of La or Nb;
rela

Assignees

• Kepler Computing Inc

Inventors

• Manipatruni Sasikanth
• Fang Yuan-Sheng
• Menezes Robert
• Dokania Rajeev Kumar
• Thareja Gaurav
• Ramesh Ramamoorthy
• Mathuriya Amrita

Classifications

• H10D1/694

  comprising noble metals or noble metal oxides · CPC title

• H10D1/682

  having dielectrics comprising perovskite structures · CPC title

• H03K19/23 Primary

  Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs · CPC title

• G06F7/501 Primary

  Half or full adders, i.e. basic adder cells for one denomination · CPC title

• H01L28/65

  Electricity · mapped topic