Customer-transparent logic redundancy for improved yield

Patent metadata

Field	Value
Publication number	US-9791507-B2
Application number	US-201614995353-A
Country	US
Kind code	B2
Filing date	Jan 14, 2016
Priority date	Nov 12, 2014
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

First claim

What is claimed is:

1. An integrated circuit structure comprising:
a plurality of latch structures including original latch structures comprising a first input configured to receive data on a first scan path and a plurality of repair latch structures which are respectively duplicates of each respective original latch within the plurality of latch structures; and
a plurality of logic structures including original logic structures comprises a first input configured to receive data on the first scan path and a plurality of repair logic structures which are respectively duplicates of each respective original logic structure within the plurality of logic structures, such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure,
wherein the plurality of latch structures is configured to provide an output indicative of whether all of the original latch structures are not defective in response to a test scan of the plurality of latch structures,
wherein, when all of the original latch structures pass the test scan, the plurality of logic structures is configured to provide an output indicative of whether all of the original logic structures pass a logic test, different than the test scan, and
wherein, when one of the original latch structures does not pass the test scan, the plurality of latch structures is configured so that one of the repair latch structures is substituted for a defective original latch structure as a repair so that the logic test is carried out on the plurality of logic structures.

2. The integrated circuit structure of claim 1 , wherein, when one of the original logic structures does not pass the logic test, the plurality of logic structures is configured such that one of the repair logic structures is substituted for a defective original logic structure as a repair.

3. The integrated circuit structure of claim 2 , wherein the plurality of logic structures are configured so that the logic test will not be carried out unless at least all of the original latch structures pass the test scan or any of the original latch structures determined to be defective is repaired by one of the repair latch structures.

4. The integrated circuit structure of claim 3 , wherein:
the plurality of latch structures further comprises a second input configured to receive functional data on a second data path comprising the repair latch structures; and
at least one of the plurality of latch structures further comprises an input multiplexer configured to receive a plurality of multiplexer select bits.

5. The integrated circuit structure of claim 4 , wherein a first select bit of the plurality of multiplexer select bits is configured to enable the first scan path such that a test vector is loaded into the first input of the plurality of latch structures.

6. The integrated circuit structure of claim 5 , wherein a second select bit of the plurality of multiplexer select bits is configured to enable the second scan path such that the test vector is loaded into the second input of the plurality of latch structures.

7. The integrated circuit structure of claim 6 , wherein the plurality of latch structures further comprise an output multiplexer configured to receive data from one of the original latch structures on the first scan path or data from one of the repair latch structures on the second scan path, and forward the data from the one of the original latch structures or the one of the repair latch structures based on the plurality of multiplexer select bits.

8. The integrated circuit structure of claim 7 , wherein the plurality of logic structures is configured to receive the data from the output multiplexer of the plurality of latch structures.

9. The integrated circuit structure of claim 6 , wherein the plurality of latch structures further comprise a first output configured to output data from one of the original latch structures on the first scan path, and a second output configured to output data from one of the repair latch structures on the second scan path.

10. The integrated circuit structure of claim 8 , wherein the plurality of logic structures is configured to receive the data output from one of the original latch structures on the first scan path at the first input of the plurality of logic structures, and receive the data output from one of the repair latch structures on the second scan path at a second input of the plurality of logic structures.

11. The integrated circuit structure of claim 1 , wherein, when one of the original latch structures does not pass the test scan, the integrated circuit structure is configured to determine whether there is a valid repair solution by determining whether a non-defective repair latch structure is available to substitute for the defective original latch structure as a repair.

12. The integrated circuit structure of claim 11 , wherein the integrated circuit structure comprises an integrated circuit chip, and wherein, when it is determined that a non-defective repair latch structure is not available to substitute for the defective original latch structure as a repair, the integrated circuit structure is configured to declare the integrated circuit chip as defective.

Assignees

• IBM

Inventors

• Arsovski Igor
• Goss John R
• Hunt-Schroeder Eric D
• Killorin Andrew K

Classifications

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title