Programmable circuits for correcting scan-test circuitry defects in integrated circuit designs

Patent metadata

Field	Value
Publication number	US-9618579-B2
Application number	US-201514697702-A
Country	US
Kind code	B2
Filing date	Apr 28, 2015
Priority date	Apr 28, 2015
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

In certain embodiments, an integrated circuit has scan-test circuitry that performs scan testing on circuitry under scan test (CUST) within the IC, where the scan-test circuitry is susceptible to a defect. In order to enable the defect to be corrected after it occurs, the scan-test circuitry includes a set of programmable circuitry connected to provide a signal to other circuitry (e.g., a scan chain) within the scan-test circuitry, where the set of programmable circuitry includes one or more configurable memory cells connected to control the programming of the set of programmable circuitry. The memory cell(s) can be configured to program the set of programmable circuitry to enable the scan testing to be performed without modification. The memory cell(s) can also be configured to program the set of programmable circuitry to modify the scan testing to correct the defect in the scan-test circuitry.

First claim

What is claimed is:

1. An integrated circuit comprising:
circuitry under scan test (CUST);
scan-test circuitry comprising:
a scan chain of interconnected scan-chain elements, wherein the scan chain supports scan testing of the CUST;
scan-test control circuitry connected to control operations of the scan chain to perform the scan testing of the CUST; and
a set of programmable circuitry configured to provide a signal based on configurable data stored in one or more configurable memory cells of the set of programmable circuitry to selectively:
enable operation of the scan chain in response to a first set of the configurable data to perform scan testing of the CUST without modification, and
adjust operation of the scan chain in response to a second set of the configurable data to perform modified scan testing of the CUST to correct a defect in the scan test circuitry.

2. The integrated circuit of claim 1 , wherein:
the defect is a hold-time violation; and
the one or more configurable memory cells are configurable to program the set of programmable circuitry to (i) delay an output signal from a previous scan flip-flop in the scan chain and (ii) selectively apply the delayed output signal to a next scan flip-flop in the scan chain to correct the hold-time violation.

3. The integrated circuit of claim 2 , wherein the set of programmable circuitry comprises a programmable delay element configurable to apply a selectable amount of delay to the output signal from the previous scan flip-flop based on one or more configuration bits stored in one or more of the configurable memory cells.

4. The integrated circuit of claim 3 , wherein the set of programmable circuitry further comprises a multiplexer connected to receive both of and selectably output one of (i) the delayed output signal from the programmable delay element and (ii) an undelayed version of the output signal from the previous scan flip-flop based on another one of the configurable memory cells.

5. The integrated circuit of claim 3 , wherein the programmable delay element is configurable to apply any of a plurality of different amounts of delay to the output signal based on a plurality of configuration bits stored in a plurality of the configurable memory cells.

6. The integrated circuit of claim 1 , wherein:
the defect is a polarity reversal in a clock signal at a boundary between two different clock distribution networks along the scan chain; and
the one or more configurable memory cells are configurable to program the set of programmable circuitry to selectively reverse the polarity of the clock signal to correct the polarity reversal.

7. The integrated circuit of claim 6 , wherein:
the scan chain comprises a lockup latch at the boundary;
the polarity reversal results from the lockup latch having a reverse polarity; and
the set of programmable circuitry comprises a logic gate that selectably inverts the clock signal applied to the lockup latch based on a configuration bit stored in a single configurable memory cell.

8. The integrated circuit of claim 7 , wherein:
the lockup latch having the reverse polarity is a negative-level lockup latch; and
the logic gate is an XNOR gate.

9. The integrated circuit of claim 7 , wherein:
the lockup latch having the reverse polarity is a positive-level lockup latch; and
the logic gate is an XOR gate.

10. The integrated circuit of claim 1 , wherein:
the defect is a polarity reversal in a constrained signal generated by another block of circuitry and applied to the scan-test control circuitry; and
the one or more configurable memory cells are configurable to program the set of programmable circuitry to selectively reverse the polarity of the constrained signal to correct the polarity reversal.

11. The integrated circuit of claim 10 , wherein the set of programmable circuitry comprises an XOR gate that selectably inverts the constrained signal based on a configuration bit stored in a single configurable memory cell.

12. The integrated circuit of claim 10 , wherein the other block of circuitry that generates the constrained signal is part of the integrated circuit.

13. A method for performing scan testing within an integrated circuit, the method comprising:
providing scan-test circuitry comprising a scan chain of interconnected scan-chain elements, scan-test control circuitry, and a set of programmable circuitry;
controlling operations of the scan chain by the scan-test control circuitry;
accessing configuration data stored in one or more configurable memory cells of the set of programmable circuitry; and
providing, by the set of programmable circuitry, a signal based on configurable data stored in one or more configurable memory cells of the set of programmable circuitry to selectively:
enable operation of the scan chain in response to a first set of the configurable data to perform scan testing of circuitry under scan test (CUST) without modification, and
adjust operation of the scan chain in response to a second set of the configurable data to perform modified scan testing of the CUST to correct a defect in the scan test circuitry.

14. The method of claim 13 , wherein:
the defect is a hold-time violation; and
the one or more configurable memory cells program the set of programmable circuitry to (i) delay an output signal from a previous scan flip-flop in the scan chain and (ii) selectively apply the delayed output signal to a next scan flip-flop in the scan chain to correct the hold-time violation.

15. The method of claim 13 , wherein:
the defect is a polarity reversal in a clock signal at a boundary between two different clock distribution networks along the scan chain; and
the one or more configurable memory cells program the set of programmable circuitry to selectively reverse the polarity of the clock signal to correct the polarity reversal.

16. The method of claim 13 , wherein:
the defect is a polarity reversal in a constrained signal generated by an other block of circuitry and applied to the scan-test control circuitry; and
the one or more configurable memory cells program the set of programmable circuitry to selectively reverse the polarity of the constrained signal to correct the polarity reversal.

Assignees

• Lattice Semiconductor Corp

Inventors

• Chakraborty Kanad

Classifications

• G01R31/3172

  Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/318588 Primary

  Security aspects · CPC title

• G01R31/318536

  Scan chain arrangements, e.g. connections, test bus, analog signals · CPC title