Three-dimensional memory device containing amorphous and crystalline blocking dielectric layers

Patent metadata

Field	Value
Publication number	US-11289416-B2
Application number	US-201916695775-A
Country	US
Kind code	B2
Filing date	Nov 26, 2019
Priority date	Nov 26, 2019
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate;
forming memory openings vertically extending through the alternating stack;
forming memory opening fill structures in the memory openings, wherein each of the memory opening fill structures comprises a memory film and a vertical semiconductor channel that extend vertically, and each memory film comprises a blocking dielectric metal oxide layer;
forming backside recesses by removing the sacrificial material layers selective to the insulating layers and the memory opening fill structures;
forming an amorphous dielectric nucleation layer including an amorphous dielectric metal oxide material directly on physically exposed surfaces of the insulating layers and directly on outer sidewalls of the blocking dielectric metal oxide layers; and
forming electrically conductive layers in remaining volumes of the backside recesses employing a nucleation process that forms a crystalline metallic liner directly on the amorphous dielectric nucleation layer.

2. The method of claim 1 , wherein the blocking dielectric metal oxide layers are formed as amorphous dielectric metal oxide layers, and are subsequently converted into crystalline blocking dielectric metal oxide layers by an anneal process.

3. The method of claim 2 , wherein the amorphous dielectric metal oxide material of the amorphous dielectric nucleation layer is deposited directly on the crystalline blocking dielectric metal oxide layers.

4. The method of claim 2 , further comprising:
forming drain regions in the memory opening fill structures at an upper end of a respective one of the semiconductor channels; and
forming source regions in, or on, upper portions of the substrate.

5. The method of claim 1 , further comprising:
forming a silicon oxide liner directly on a sidewall of each memory opening, wherein each of the blocking dielectric metal oxide layers is formed directly on the silicon oxide liner within a respective one of the memory openings; and
removing portions of the silicon oxide liner that are located at levels of the backside recesses without removing portions of the silicon oxide liner that are located at levels of the insulating layers after formation of the backside recesses,
wherein sidewall segments of the blocking dielectric metal oxide layers are physically exposed to the backside recesses; and
wherein the amorphous dielectric nucleation layer is formed directly on surfaces of remaining segments of the silicon oxide liner that remain at levels of the insulating layers.

6. The method of claim 1 , further comprising forming a blocking dielectric semiconductor compound layer on a respective one of the blocking dielectric metal oxide layers within each of the memory openings.

7. The method of claim 6 , further comprising forming a charge storage layer and a tunneling dielectric layer on a respective one of the blocking dielectric semiconductor compound layers within each of the memory openings, wherein each of the memory films comprises a respective blocking dielectric metal oxide layer, a respective blocking dielectric semiconductor compound layer, a respective charge storage layer, and a respective tunneling dielectric layer, and wherein each of the semiconductor channels is formed on a respective one of the tunneling dielectric layers.

8. The method of claim 1 , wherein:
each of the blocking dielectric metal oxide layers consists essentially of a first aluminum oxide material; and
the amorphous dielectric nucleation layer consists essentially of a second aluminum oxide material in an amorphous phase.

9. The method of claim 8 , wherein:
the first aluminum oxide material is deposited in an amorphous phase and is subsequently converted into a polycrystalline aluminum oxide material prior to formation of the amorphous dielectric nucleation layer; and
the amorphous dielectric nucleation layer is deposited in an amorphous phase and remains amorphous until after formation of the electrically conductive layers.

10. The method of claim 9 , wherein:
wherein each of the blocking dielectric metal oxide layers is thicker than the amorphous dielectric nucleation layer;
the amorphous dielectric nucleation layer has a thickness in a range from 0.3 nm to 1 nm; and
the crystalline metallic liner comprises a conductive metallic nitride material.

11. The method of claim 1 , further comprising:
forming backside trenches through the alternating stack after formation of the memory opening fill structures;
isotropically etching the sacrificial material layers selective to the insulating layers and the memory opening fill structures by introducing an isotropic etchant into the backside trenches;
conformally depositing the amorphous dielectric nucleation layer on physically exposed surfaces of the backside trenches and the backside recesses; and
filling remaining volumes of the backside recesses with a conductive fill material after formation of the crystalline metallic liner on the amorphous dielectric nucleation layer.

12. The method of claim 1 , further comprising:
forming stepped surfaces in a staircase region by patterning the alternating stack;
forming a retro-stepped dielectric material portion of the stepped surfaces of the alternating stack; and
forming contact via structures on a respective one of the electrically conducive layers through the retro-stepped dielectric material portion.

13. A semiconductor structure comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
memory openings vertically extending through the alternating stack;
memory opening fill structures located in the memory openings, wherein each of the memory opening fill structures comprises a memory film and a vertical semiconductor channel that extend vertically, and each memory film comprises a crystalline blocking dielectric metal oxide layer; and
a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers, wherein each of the electrically conductive layers is in direct contact with the metal oxide amorphous dielectric nucleation layer.

14. The semiconductor structure of claim 13 , wherein each of the electrically conductive layers comprises a respective crystalline metallic nitride liner that contacts the amorphous dielectric nucleation layer and respective tungsten conductive fill material portion that is embedded in the respective crystalline metallic nitride liner.

15. The semiconductor structure of claim 13 , wherein the amorphous dielectric nucleation layer contacts a sidewall of the blocking dielectric metal oxide layer in the memory opening fill structure.

16. The semiconductor structure of claim 13 , further comprising drain regions located in the memory opening fill structures and contacting an upper end of a respective one of the semiconductor channels.

17. The semiconductor structure of claim 13 , wherein each of the memory opening fill structures comprises:
a silicon oxide blocking dielectric layer located on a respective one of the crystalline blocking dielectric metal oxide layers; and
vertical stacks of silicon oxide liners contacting an outer sidewall of the respective one of the crystalline blocking dielectric metal oxide layers and located a

Assignees

• Sandisk Technologies Llc

Inventors

• Tsutsumi Masanori
• Hosoda Naohiro
• Hamaguchi Shuichi
• Isozumi Kazuki
• Mizuno Genta
• Mukae Yusuke
• Nakamura Ryo
• Ueda Yu

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H10D64/037 Primary

  comprising charge-trapping insulators · CPC title

• H01L23/53223

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic