Photodetector with superconductor nanowire transistor based on interlayer heat transfer

Patent metadata

Field	Value
Publication number	US-11283001-B2
Application number	US-202117195522-A
Country	US
Kind code	B2
Filing date	Mar 8, 2021
Priority date	Jul 28, 2017
Publication date	Mar 22, 2022
Grant date	Mar 22, 2022

Abstract

A transistor includes (i) a first wire including a semiconducting component configured to operate in an on state at temperatures above a semiconducting threshold temperature and (ii) a second wire including a superconducting component configured to operate in a superconducting state while: a temperature of the superconducting component is below a superconducting threshold temperature and a first input current supplied to the superconducting component is below a current threshold. The semiconducting component is located adjacent to the superconducting component. In response to a first input voltage, the semiconducting component is configured to generate an electromagnetic field sufficient to lower the current threshold such that the first input current exceeds the lowered current threshold.

First claim

What is claimed is:

1. A transistor, comprising:
a first wire including a semiconducting component configured to operate in an on state at temperatures above a semiconducting threshold temperature; and
a second wire including a superconducting component configured to operate in a superconducting state while:
a temperature of the superconducting component is below a superconducting threshold temperature; and
a first input current supplied to the superconducting component is below a current threshold;

wherein the semiconducting component is located adjacent to the superconducting component;
wherein, in response to a first input voltage, the semiconducting component is configured to generate an electromagnetic field sufficient to lower the current threshold such that the first input current exceeds the lowered current threshold, thereby transitioning the superconducting component to a non-superconducting state;
wherein the transistor is configured to operate in an on state while the superconducting component is in the superconducting state; and
wherein the transistor is configured to operate in an off state while the superconducting component is in the non-superconducting state.

2. The transistor of claim 1 , wherein the semiconducting component comprises a gate of the transistor and the superconducting component comprises a source and drain of the transistor.

3. The transistor of claim 1 , wherein the superconducting component comprises a superconducting nanowire.

4. The transistor of claim 3 , wherein the superconducting nanowire has a constricted region at a location adjacent to the semiconducting component.

5. The transistor of claim 1 , wherein the transistor is configured to operate in a second mode, wherein, in the second mode:
in response to the first input current exceeding the current threshold, the superconducting component is configured to generate heat sufficient to increase a temperature of the semiconducting component above the semiconducting threshold temperature;
the transistor is configured to operate in an off state while the semiconducting component is maintained at a temperature below the semiconducting threshold temperature; and
the transistor is configured to operate in an on state while the semiconducting component is at a temperature above the semiconducting threshold temperature.

6. The transistor of claim 5 , wherein, in the second mode, the superconducting component is configured to generate heat at a location adjacent to the semiconducting component during a transition from the superconducting state to a non-superconducting state.

7. The transistor of claim 5 , wherein, in the second mode, the superconducting component comprises a gate of the transistor and the semiconducting component comprises a source and drain of the transistor.

8. The transistor of claim 1 , wherein the superconducting component is electrically isolated from the semiconducting component.

9. The transistor of claim 1 , wherein the semiconducting component is composed of Germanium.

10. The transistor of claim 1 , wherein the semiconducting component has a first region in proximity to the superconducting component and secondary regions neighboring the first region.

11. The transistor of claim 10 , wherein the first region is configured to operate in the on state at temperatures above the semiconducting threshold temperature and the secondary regions are configured to operate in the on state at temperatures above a second semiconducting threshold temperature, the second semiconducting threshold temperature being below the semiconducting threshold temperature.

12. The transistor of claim 10 , wherein the first region is narrower than the secondary regions.

13. A method for operating a superconductor-based transistor, comprising:
operating the superconductor-based transistor in a first mode, including:
maintaining the superconductor-based transistor in an off state, including:
maintaining a superconducting component of the superconductor-based transistor in a superconducting state; and
maintaining a semiconducting component of the superconductor-based transistor in an off state; and

transitioning the superconductor-based transistor from the off state to an on state, including supplying current to the superconducting component, wherein the current exceeds a superconducting current threshold for the superconducting component;
wherein, in response to the current supplied to the superconducting component, the superconducting component transitions to a non-superconducting state and generates heat sufficient to increase a temperature of the semiconducting component above a semiconducting threshold temperature and enable current flow through the semiconducting component.

14. The method of claim 13 , wherein maintaining the superconductor-based transistor in the off state comprises maintaining the superconducting component at a temperature below a superconducting temperature.

15. The method of claim 13 , wherein maintaining the superconductor-based transistor in an off state comprises supplying a current to the superconducting component that is below the superconducting current threshold.

16. The method of claim 13 , further comprising operating the superconductor-based transistor in a second mode, including, while in the second mode:
maintaining the superconductor-based transistor in an on state, including:
maintaining a superconducting component of the superconductor-based transistor in a superconducting state;
supplying a first current to the superconducting component, the first current below a current threshold for the superconducting component; and
maintaining a semiconducting component of the superconductor-based transistor in an off state; and

transitioning the superconductor-based transistor from the on state to an off state, including supplying a voltage to the semiconducting component;
wherein, in response to the voltage, the semiconducting component is configured to generate an electromagnetic field sufficient to lower the current threshold such that the first current exceeds the lowered current threshold, thereby transitioning the superconducting component to a non-superconducting state.

17. A transistor, comprising:
a first wire including a semiconducting component configured to operate in an on state at temperatures above a semiconducting threshold temperature; and
a second wire located adjacent to the semiconducting component;
wherein, in response to an input current, the second wire is configured to generate heat sufficient to increase a temperature of the semiconducting component above the semiconducting threshold temperature;
wherein the transistor is configured to operate in an off state while the semiconducting component is maintained at a temperature below the semiconducting threshold temperature, and
wherein the transistor is configured to operate in an on state while the semiconducting component is at a temperature above the semiconducting threshold temperature.

18. The transistor of claim 17 , wherein the second wire comprises a gate of the transistor and the semiconducting component comprises a source and drain of the transistor.

19. The transistor of claim 17 , wherein the second wire comprises a superconducting component maintained in a non-superconducting state.

20. The transistor of claim 17 , wherein the second wire has a constricted region at a location adjacent to the semiconducting component.

21. The transistor of claim 17 , wherein the second w

Assignees

• Psiquantum Corp

Inventors

• Najafi Faraz

Classifications

• H10D64/608 Primary

  being superconducting · CPC title

• H10D30/6733

  Multi-gate TFTs · CPC title

• H10F99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10F77/206

  for devices having potential barriers · CPC title

• H10F30/282

  Insulated-gate field-effect transistors [IGFET], e.g. MISFET [metal-insulator-semiconductor field-effect transistor] phototransistors · CPC title