Bottom-gate thin-body transistors for stacked wafer integrated circuits

Patent metadata

Field	Value
Publication number	US-2016353038-A1
Application number	US-201514723719-A
Country	US
Kind code	A1
Filing date	May 28, 2015
Priority date	May 28, 2015
Publication date	Dec 1, 2016
Grant date	—

Abstract

An integrated circuit die may include bottom-gate thin-body transistors. The bottom-gate thin-body transistors may be formed in a thinned-down substrate having a thickness that is defined by shallow trench isolation structures that provide complete well isolation for the transistors. The transistors may include gate terminal contacts formed through the shallow trench isolation structures, bulk terminal contacts that are formed through the thinned substrate and that overlap with the gate contacts, and source-drain terminal contacts with in-situ salicide. Additional metallization layers may be formed over the gate/bulk/source-drain contacts after bonding.

First claim

What is claimed is:

1 . A transistor in an integrated circuit, comprising:
a substrate having a first surface and a second surface; a gate conductor formed over the first surface of the substrate; and a gate terminal contact that is formed over the second surface of the substrate.

2 . The transistor defined in claim 1 , further comprising:
a dielectric layer interposed between the substrate and the gate terminal contact.

3 . The transistor defined in claim 1 , further comprising:
a shallow trench isolation structure formed in the substrate, wherein the gate terminal contact is coupled to the gate conductor through the shallow trench isolation structure, and wherein the shallow trench isolation structure defines the thickness of the substrate.

4 . The transistor defined in claim 3 , further comprising:
an additional shallow trench isolation structure that is formed in the substrate and that has a different depth than the shallow trench isolation structure.

5 . The transistor defined in claim 4 , further comprising:
a body terminal contact that is formed over the second surface of the substrate and directly over the additional shallow trench isolation structure, wherein the body terminal contact has a length that is substantially equal to the thickness of the dielectric layer.

6 . The transistor defined in claim 5 , wherein the body terminal contact overlaps directly with the gate conductor.

7 . The transistor defined in claim 1 , further comprising:
source-drain diffusion regions that are formed in the substrate and extends between the first and second surfaces; and source-drain terminal contacts that are formed over the second surface of the substrate and that are in-situ salicided at the second surface of the substrate.

8 . The transistor defined in claim 7 , further comprising:
salicide formed on the source-drain diffusion regions at the first surface of the substrate.

9 . The transistor defined in claim 1 , further comprising:
a plurality of metallization layers formed above the gate terminal contact over the second surface of the substrate.

10 . A method of forming transistor structures on a substrate having first and second opposing surfaces, comprising:
forming a gate conductor on the first surface of the substrate; thinning the substrate from its second surface; and after thinning the substrate, forming a gate terminal contact through the second surface of the substrate.

11 . The method defined in claim 10 , further comprising:
forming a dielectric layer on the gate conductor over the first surface of the substrate; and bonding the dielectric layer to a carrier wafer prior to thinning the substrate.

12 . The method defined in claim 10 , further comprising:
forming a shallow trench isolation structure in the substrate; and forming a contact hole through the shallow trench isolation structure for connecting the gate conductor to the gate terminal contact.

13 . The method defined in claim 10 , further comprising:
forming a source-drain diffusion region in the substrate; after thinning the substrate, forming a source-drain terminal contact over the second surface of the substrate; forming a contact hole for connecting the source-drain diffusion region to the source-drain terminal contact; and depositing silicide material at least partially within the contact hole at the second surface of the substrate.

14 . The method defined in claim 10 , further comprising:
simultaneously doping a channel region and a bulk region in the substrate.

15 . The method defined in claim 10 , further comprising:
forming a first gate insulating layer interposed between the gate conductor and the first surface of the substrate; and forming a second gate insulating layer that is different in thickness than the first gate insulating layer.

16 . A system, comprising:
a central processing unit; memory; a lens; input-output circuitry; and an imaging device, wherein the imaging device comprises:
a first die; and
a second die that is bonded to the first die, wherein the second die includes a bottom-gate thin-body transistor.

17 . The system defined in claim 16 , wherein the bottom-gate thin-body transistor is formed on a substrate having a thickness that is defined by a shallow trench isolation structure formed in the substrate.

18 . The system defined in claim 17 , wherein the bottom-gate thin-body transistor has salicide material formed at top and bottom surfaces of the substrate.

19 . The system defined in claim 17 , wherein the bottom-gate thin-body transistor has a gate that is formed on a first surface of the substrate and a plurality of metallization layers that is formed on a second opposing surface of the substrate.

20 . The system defined in claim 16 , wherein the first die includes photodiodes configured in a backside illumination (BSI) arrangement.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Madurawe Raminda
• Soleimani Hamid
• Rahim Irfan

Classifications

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L29/78696

  Electricity · mapped topic

• H01L29/66742

  Electricity · mapped topic