Method and system for generating a ramping signal

Patent metadata

Field	Value
Publication number	US-11272134-B2
Application number	US-202017127128-A
Country	US
Kind code	B2
Filing date	Dec 18, 2020
Priority date	Dec 12, 2013
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

A system is provided for generating a ramping signal. The system includes a plurality of storage circuits each including an input and an output. The output of a previous storage circuit is connected to the input of a next storage circuit. The storage circuits are configured to propagate a first enable signal based on a first control signal. The system also includes a plurality of first current generating circuits. Each first current generating circuit is coupled to the output of a corresponding storage circuit to receive the propagated first enable signal. The first current generating circuits are configured to generate a first current signal based on the propagated first enable signal.

First claim

What is claimed is:

1. A system for generating a ramping signal, comprising:
a plurality of storage circuits each including an input and an output, the output of a previous storage circuit being connected to the input of a next storage circuit, the storage circuits being configured to propagate a ramp enable signal, each of the storage circuits being configured to output a respective first enable signal;
a plurality of first current generating circuits, each configured to generate a respective first current based on a respective first enable signal and a respective first bias signal;
a plurality of second current generating circuits, each configured to generate a respective second current based on a respective second enable signal and a respective second bias signal, wherein the respective first and second bias signals are the same, and wherein the respective first and second enable signals are the same; and
an offset circuit configured to generate an offset current based on the second currents;
wherein the ramping signal is generated based on the first currents and the offset current.

2. The system of claim 1 , further comprising:
a load block configured to generate the ramping signal based on the first currents and the offset current.

3. The system of claim 2 , further comprising:
a control circuit block configured to control a resistance of the load block, wherein
the load block is configured to generate the ramping signal based on the first currents, the offset current, and the resistance of the load block.

4. The system of claim 1 , wherein:
the storage circuits are configured to propagate the ramp enable signal according to a clock signal; and
a slope of the ramping signal is adjustable based on adjusting the frequency of the clock signal.

5. The system of claim 1 , wherein each of the storage circuits includes a latch, and wherein a first latch of the latches receives the ramp enable signal.

6. The system of claim 5 , wherein the latches are gated D latches, clocked D latches, or edge triggering registers.

7. The system of claim 1 , wherein each of the first current generating circuits comprises:
one or more transistors, wherein a gate of one of the transistors in each of the first current generating circuits is coupled to an output of a respective storage circuit.

8. A system for generating a ramping signal, comprising:
a plurality of storage circuits each including an input and an output, the output of a previous storage circuit being connected to the input of a next storage circuit, the storage circuits being configured to propagate a ramp enable signal, each of the storage circuits being configured to output a respective first enable signal;
a plurality of first current generating circuits, each configured to generate a respective first current based on a respective first enable signal and a respective first bias signal;
a plurality of second current generating circuits, each configured to generate a respective second current based on a respective second enable signal and a respective second bias signal, wherein the respective first and second bias signals are not the same, and wherein the respective first and second enable signals are not the same; and
an offset circuit configured to generate an offset current based on the second currents;
wherein the ramping signal is generated based on the first currents and the offset current.

9. The system of claim 8 , further comprising:
a load block configured to generate the ramping signal based on the first currents and the offset current.

10. The system of claim 9 , further comprising:
a control circuit block configured to control a resistance of the load block, wherein the load block is configured to generate the ramping signal based on the first currents, the offset current, and the resistance of the load block.

11. The system of claim 8 , wherein:
the storage circuits are configured to propagate the ramp enable signal according to a clock signal; and
a slope of the ramping signal is adjustable based on adjusting the frequency of the clock signal.

12. The system of claim 8 , wherein each of the storage circuits includes a latch, and wherein a first latch of the latches receives the ramp enable signal.

13. The system of claim 12 , wherein the latches are gated D latches, clocked D latches, or edge triggering registers.

14. The system of claim 8 , wherein each of the first current generating circuits comprises:
one or more transistors, wherein a gate of one of the transistors in each of the first current generating circuits is coupled to an output of a respective storage circuit.

15. A system for generating a ramping signal, comprising:
a plurality of storage circuits each including an input and an output, the output of a previous storage circuit being connected to the input of a next storage circuit, the storage circuits being configured to propagate a ramp enable signal, each of the storage circuits being configured to output a respective first enable signal;
a plurality of first current generating circuits, each configured to generate a respective first current based on a respective first enable signal and a respective first bias signal;
a plurality of second current generating circuits, each configured to generate a respective second current based on a respective second enable signal and a respective second bias signal, wherein the respective first and second bias signals are not the same, and wherein the respective first and second enable signals are the same; and
an offset circuit configured to generate an offset current based on the second currents;
wherein the ramping signal is generated based on the first currents and the offset current.

16. The system of claim 15 , further comprising:
a load block configured to generate the ramping signal based on the first currents and the offset current.

17. The system of claim 16 , further comprising:
a control circuit block configured to control a resistance of the load block, wherein the load block is configured to generate the ramping signal based on the first currents, the offset current, and the resistance of the load block.

18. The system of claim 15 , wherein:
the storage circuits are configured to propagate the ramp enable signal according to a clock signal; and
a slope of the ramping signal is adjustable based on adjusting the frequency of the clock signal.

19. The system of claim 15 , wherein each of the storage circuits includes a latch, and wherein a first latch of the latches receives the ramp enable signal.

20. The system of claim 15 , wherein each of the first current generating circuits comprises:
one or more transistors, wherein a gate of one of the transistors in each of the first current generating circuits is coupled to an output of a respective storage circuit.

Assignees

• Cista Sys Corp

Inventors

• Lee Dennis Tunglin
• Zhang Guangbin

Classifications

• H03K4/02 Primary

  having stepped portions, e.g. staircase waveform · CPC title

• H03K4/08 Primary

  having sawtooth shape · CPC title

• H04N25/673

  by using reference sources · CPC title

• H04N25/677

  for reducing the column or line fixed pattern noise · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title