Method and system for generating a ramping signal

Patent metadata

Field	Value
Publication number	US-10440303-B2
Application number	US-201815865326-A
Country	US
Kind code	B2
Filing date	Jan 9, 2018
Priority date	Dec 12, 2013
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

A system is provided for generating a ramping signal. The system includes a plurality of storage circuits each including an input and an output. The output of a previous storage circuit is connected to the input of a next storage circuit. The storage circuits are configured to propagate a first enable signal based on a first control signal. The system also includes a plurality of first current generating circuits. Each first current generating circuit is coupled to the output of a corresponding storage circuit to receive the propagated first enable signal. The first current generating circuits are configured to generate a first current signal based on the propagated first enable signal.

First claim

What is claimed is:

1. A system for generating a ramping signal, comprising:
a ramp segment comprising:
a plurality of storage circuits each including an input and an output, the output of a previous storage circuit coupled to the input of a next storage circuit, the storage circuits each being configured to generate a first signal; and
a plurality of first circuits each coupled to the output of a corresponding storage circuit of the plurality of storage circuits, the first circuits each being configured to receive the first signal from the corresponding storage circuit, generate a second signal based at least on the received first signal, and generate a ramp current signal based on the generated second signals; and
an offset segment comprising:
a plurality of second circuits each coupled to an offset enable signal and a bias signal to generate an offset current signal, wherein the ramping signal is based at least on the generated ramp current signal from the each first circuit and the generated offset current signal from the each second circuit.

2. The system of claim 1 , wherein:
the storage circuits comprises a first storage circuit and a plurality of second storage circuits connected in series;
the first storage circuit is configured to receive a clock signal and a ramp enable signal, and to generate the corresponding first signal as the output based at least on the clock signal and the ramp enable signal; and
each of the second storage circuits is configured to receive the clock signal and the corresponding output from the previous storage circuit, and to generate the corresponding first signal as the output based at least on the clock signal and the corresponding output from the previous storage circuit.

3. The system of claim 1 , wherein:
the output of the each storage circuit couples to one of the first circuits that correspondingly obtains the first signal;
each of the first circuits is configured to further receive another bias signal and generate a part of the ramp current signal based at least on the obtained first signal and the another bias signal; and
each of the first circuits is configured to generate the part of the ramp current signal in response to the another bias signal turning on the each first circuit.

4. The system of claim 1 , wherein:
transistors of the second circuit are smaller than transistors of the first circuit in at least one of width or length.

5. The system of claim 1 , wherein:
a ramp signal generator comprises one or more of the ramp segments and one or more of the offset segments evenly distributed in a current generating circuit block of the ramp signal generator; and
the ramp signal generator has a longitudinal shape extending along an edge of a pixel grid.

6. The system of claim 5 , wherein:
the ramp signal generator couples to one or more comparators;
the each comparator couples to a column read circuit of the pixel grid to receive a readout signal; and
the each comparator is configured to compare the readout signal with the ramping signal.

7. The system of claim 5 , wherein:
the ramp signal generator further comprises a load block coupled to the current generating circuit block;
the load block is configured to convert the ramp current signal to a first component of the ramping signal; and
the load block is configured to convert the offset current signal to a second component of the ramping signal.

8. The system of claim 7 , wherein:
the ramp signal generator further comprises a load block coupled to the current generating circuit block;
the control circuit block is configured to provide control signals for the current generating circuit block and the load block;
the control signals are associated with at least one of:
a clock signal for the ramp segment, a ramp enable signal for the ramp segment, an offset enable signal for the offset segment, or a bias signal for the offset segment;
the ramp enable signal selectively turns on one or more of the first circuits that receive the ramp enable signal; and
the offset enable signal selectively turns on one or more of the second circuits that receive the offset enable signal.

9. A sensor device, comprising a pixel grid and a ramp signal generator coupled together, wherein:
the ramp signal generator comprises a current generating circuit block;
the current generating circuit block comprises a ramp segment;
the ramp segment comprises:
a plurality of storage circuits each including an input and an output, the output of a previous storage circuit coupled to the input of a next storage circuit, the storage circuits each being configured to generate a first signal; and
a plurality of first circuits each coupled to the output of a corresponding storage circuit of the plurality of storage circuits, the first circuits each being configured to receive the first signal from the corresponding storage circuit, generate a second signal based at least on the received first signal, and generate a ramp current signal based on the generated second signals;
the ramp signal generator is configured to convert the ramp current signal to a ramping voltage signal; and
the pixel grid is configured to obtain the ramping voltage signal as a reference signal;
wherein:
the current generating circuit block further comprises an offset segment; and
the offset segment comprises a plurality of second circuits each coupled to an offset enable signal and a bias signal to generate an offset current signal, and
the ramp signal generator is configured to combine the generated ramp current signal from the each first circuit and the generated offset current signal from the each second circuit to obtain the ramping voltage signal.

10. The sensor device of claim 9 , wherein:
the ramp signal generator further comprises a load block coupled to the current generating circuit block;
the load block is configured to convert the ramp current signal to a first component of the ramping voltage signal; and
the load block is configured to convert the offset current signal to a second component of the ramping voltage signal.

11. The sensor device of claim 9 , wherein:
the ramp signal generator further comprises a control circuit block coupled to the current generating circuit block and the load block;
the control circuit block is configured to provide control signals for the current generating circuit block and the load block;
the control signals are associated with at least one of:
a clock signal for the ramp segment, a ramp enable signal for the ramp segment, an offset enable signal for the offset segment, or a bias signal for the offset segment;
the ramp enable signal selectively turns on one or more of the first circuits that receive the ramp enable signal; and
the offset enable signal selectively turns on one or more of the second circuits that receive the offset enable signal.

12. The sensor device of claim 9 , wherein:
the storage circuits comprises a first storage circuit and a plurality of second storage circuits connected in series;
the first storage circuit is configured to receive a clock signal and a ramp enable signal, and to generate the corresponding first signal as the output based at least on the clock signal and the ramp enable signal; and
each of the second storage circuits is configured to receive the clock signal and the corresponding output from the previous storage circuit, and to generate the corresponding first signal as the output based at least on the clock signal and the corresponding output from the previous storage circuit.

13. The sensor device of claim 9 , wherein:
the output of the each storage circuit couples to

Assignees

• Cista Sys Corp

Inventors

• Lee Dennis Tunglin
• Zhang Guangbin

Classifications

• H03K4/02 Primary

  having stepped portions, e.g. staircase waveform · CPC title

• H04N25/673

  by using reference sources · CPC title

• H04N25/677

  for reducing the column or line fixed pattern noise · CPC title

• H03K4/08 Primary

  having sawtooth shape · CPC title

• H03K4/26

  in which a sawtooth current is produced through an inductor · CPC title