Method and system for generating a ramping signal

Patent metadata

Field	Value
Publication number	US-9584102-B2
Application number	US-201414560371-A
Country	US
Kind code	B2
Filing date	Dec 4, 2014
Priority date	Dec 12, 2013
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

A system is provided for generating a ramping signal. The system includes a plurality of storage circuits each including an input and an output. The output of a previous storage circuit is connected to the input of a next storage circuit. The storage circuits are configured to propagate a first enable signal based on a first control signal. The system also includes a plurality of first current generating circuits. Each first current generating circuit is coupled to the output of a corresponding storage circuit to receive the propagated first enable signal. The first current generating circuits are configured to generate a first current signal based on the propagated first enable signal.

First claim

What is claimed is:

1. A system for generating a ramping signal, comprising:
a plurality of storage circuits each including an input and an output, the output of a previous storage circuit being connected to the input of a next storage circuit, the storage circuits being configured to propagate a first enable signal based on a first control signal;
a plurality of first current generating circuits, each being coupled to the output of a corresponding storage circuit to receive the propagated first enable signal, the first current generating circuits being configured to generate a first current signal based on the propagated first enable signal; and
a load block coupled to the first current generating circuits for generating at least a first component of the ramping signal based on the first current signal, wherein a slope of the ramping signal is adjustable based on adiusting at least one of: the first current signal, a resistance of the load block, or a length of the ramping signal.

2. The system of claim 1 , wherein the first component of the ramping signal has a staircase shape or a smooth ramp curve.

3. The system of claim 1 , wherein each of the storage circuits includes a latch, and wherein a first latch receives the enable signal.

4. The system of claim 3 , wherein the latches are gated D latches or edge triggering registers and the first control signal includes a clock signal.

5. The system of claim 1 , wherein each of the first current generating circuits includes one or more transistors and a gate of one transistor is coupled to an output of the corresponding storage circuit to receive the propagated first enable signal.

6. The system of claim 1 , further comprising:
one or more second current generating circuits configured to generate a second current signal.

7. The system of claim 1 , further comprising one or more second current generating circuits configured to generate a second current signal, wherein the one or more second current generating circuits are connected to the load block to convert the second current signal to a second component of the ramping signal.

8. The system of claim 7 , further comprising one or more comparators each coupled to a column read circuit of an image sensor to receive a readout signal, wherein the comparator compares the readout signal with the ramping signal.

9. The system of claim 8 , further comprising a counter coupled to the comparator, wherein the counter records a value corresponding to the ramping signal when the comparator switches its comparing result.

10. The system of claim 1 , wherein the ramping signal is a linear curve or a non-linear curve.

11. A method for generating a ramping signal comprising:
applying a first enable signal to a series of storage circuits, each of the storage circuits including an input and an output, the output of a previous storage circuit being coupled to the input of a next storage circuit;
applying a clock signal to the series of storage circuits, wherein the clock signal enables the series of storage circuits to propagate the first enable signal through the series of storage circuits;
generating a first current signal based on the propagated first enable signal, wherein the first current signal increases every time when the first enable signal propagates through a storage circuit;
converting the first current signal to a voltage signal to generate at least a first component of the ramping signal;
comparing a column readout signal from a pixel to the ramping signal; and
recording a value corresponding to the ramping signal when the comparing result changes.

12. The method of claim 11 , wherein the first component of the ramping signal has a staircase shape or a smooth ramp curve.

13. The method of claim 11 , further comprising:
generating a second current signal; and
converting the first and second current signal to a voltage signal to generate the ramping signal.

14. The method of claim 11 , wherein each of the series of storage circuits includes a latch.

15. The method of claim 14 , wherein the latch is a gated D latch or an edge triggered register.

16. A system for generating a ramping signal, the system comprising:
a plurality of latches connected in series and configured to propagate a first enable signal based on a clock signal;
a plurality of first current generating circuits coupled to outputs of the latches, the first current generating circuits being configured to generate a first current signal based on the propagated first enable signal;
one or more second current generating circuits configured to generate a second current signal; and
a load block coupled to the plurality of first current generating circuits and the one or more second current generating circuits, wherein the load block converts the first and second current signal to a voltage signal to generate the ramping signal, wherein a slope of the ramping signal is adjustable based on adjusting at least one of: the first current signal, a resistance of the load block, or a length of the ramping signal.

17. A system for generating a ramping signal, comprising:
a plurality of storage circuits each including an input and an output, the output of a previous storage circuit being connected to the input of a next storage circuit, the storage circuits being configured to propagate a first enable signal based on a first control signal; and
a plurality of first current generating circuits, each being coupled to the output of a corresponding storage circuit to receive the propagated first enable signal, the first current generating circuits being configured to generate a first current signal based on the propagated first enable signal, wherein each of the first current generating circuits includes a bias transistor and a select transistor, a gate terminal of the bias transistor being coupled to a bias signal and a gate terminal of the select transistor being coupled to the propagated first enable signal.

Assignees

• Cista Sys Corp

Inventors

• Lee Dennis Tunglin
• Zhang Guangbin

Classifications

• H03K4/02 Primary

  having stepped portions, e.g. staircase waveform · CPC title

• H04N25/673

  by using reference sources · CPC title

• H04N25/677

  for reducing the column or line fixed pattern noise · CPC title

• H03K4/08 Primary

  having sawtooth shape · CPC title

• H03K4/26

  in which a sawtooth current is produced through an inductor · CPC title