Method and system for generating a ramping signal

Patent metadata

Field	Value
Publication number	US-9894307-B2
Application number	US-201715410498-A
Country	US
Kind code	B2
Filing date	Jan 19, 2017
Priority date	Dec 12, 2013
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A system is provided for generating a ramping signal. The system includes a plurality of storage circuits each including an input and an output. The output of a previous storage circuit is connected to the input of a next storage circuit. The storage circuits are configured to propagate a first enable signal based on a first control signal. The system also includes a plurality of first current generating circuits. Each first current generating circuit is coupled to the output of a corresponding storage circuit to receive the propagated first enable signal. The first current generating circuits are configured to generate a first current signal based on the propagated first enable signal.

First claim

What is claimed is:

1. A system for generating a ramping signal, comprising:
a plurality of storage circuits each including an input and an output, the output of a previous storage circuit being connected to the input of a next storage circuit, the storage circuits being configured to propagate a first signal; and
a plurality of first circuits, each being coupled to the output of a corresponding storage circuit to receive the propagated first signal and to generate a second signal based at least on the received propagated first signal, the first circuits being configured to obtain a ramp current signal based on the generated second signals, wherein:
each of the first circuits includes a first transistor and a second transistor connected in series;
a gate terminal of the first transistor is coupled to a bias signal different from the outputs of the plurality of storage circuits; and
a gate terminal of the second transistor is coupled to the propagated first signal.

2. The system of claim 1 , wherein the first transistor includes a bias transistor and the second transistor includes a select transistor.

3. The system of claim 2 , further comprising one or more second circuits configured to generate a third signal, wherein the one or more second circuits are connected to the load block to convert the third signal to a second component of the ramping voltage signal.

4. The system of claim 3 , further comprising one or more comparators each coupled to a column read circuit of an image sensor to receive a readout signal, wherein the comparator compares the readout signal with the ramping voltage signal.

5. The system of claim 4 , further comprising a counter coupled to the comparator, wherein the counter records a value corresponding to the ramping voltage signal when the comparator switches its comparing result.

6. The system of claim 1 , wherein:
the plurality of storage circuits are connected to each other in a series; and
a first of the plurality of storage circuits is configured to receive a ramp enable signal.

7. The system of claim 1 , wherein a drain terminal of the second transistor is configured to output the second signal.

8. The system of claim 1 , further comprising:
a load block coupled to the second generating circuits for generating at least a first component of a ramping voltage signal based on the ramp current signal, wherein a slope of the ramping voltage signal is adjustable based on adjusting at least one of: the second signal, a resistance of the load block, or a length of the ramping voltage signal.

9. The system of claim 1 , wherein the first component of the ramping voltage signal has a staircase shape or a smooth ramp curve.

10. The system of claim 1 , wherein each of the storage circuits includes a latch, and wherein a first latch receives the first signal.

11. The system of claim 10 , wherein the latches are gated D latches or edge triggering registers and the first control signal includes a clock signal.

12. The system of claim 1 , wherein each of the first circuits includes one or more transistors and a gate of one transistor is coupled to an output of the corresponding storage circuit to receive the propagated first signal.

13. A system for generating a ramping signal, comprising:
a plurality of storage circuits each including an input and an output, the output of a previous storage circuit being connected to the input of a next storage circuit, the storage circuits being configured to propagate a first signal;
a plurality of first circuits, each being coupled to the output of a corresponding storage circuit to receive the propagated first signal and to generate a second signal based at least on the received propagated first signal, the first circuits being configured to obtain a ramp current signal based on the generated second signals; and
a load block coupled to the first circuits for generating at least a part of a ramping voltage signal based on the obtained ramp current, wherein a slope of the ramping voltage signal is adjustable based on adjusting at least one of: the second signal, a resistance of the load block, or a length of the voltage ramping signal.

14. The system of claim 13 , wherein the part of the ramping voltage signal has a staircase shape or a smooth ramp curve.

15. The system of claim 13 , further comprising one or more second circuits configured to generate a third signal, wherein the generated part of the ramping voltage is a first component of the ramping voltage signal, and the one or more second circuits are connected to the load block to convert the third signal to a second component of the ramping voltage signal.

16. The system of claim 15 , wherein:
the load block is coupled to the second circuits; and
the load block is configured to combine currents from the first and second circuits to generate the ramping voltage signal.

17. A system for generating a ramping signal, comprising:
a plurality of storage circuits each including an input and an output, the output of a previous storage circuit being connected to the input of a next storage circuit, the storage circuits being configured to propagate a first signal;
a plurality of first circuits, each being coupled to the output of a corresponding storage circuit to receive the propagated first signal and to generate a second signal based at least on the received propagated first signal, the first circuits being configured to obtain a ramp current signal based on the generated second signals; and
a load block coupled to the first circuits and including one or more resistors configured to convert the obtained ramp current signal to at least a first component of a ramping voltage signal.

18. The system of claim 17 , further comprising a control circuit block configured to control a total equivalent resistance of the one or more resistors.

19. The system of claim 17 , further comprising one or more second circuits configured to generate a third signal, wherein the one or more second circuits are connected to the load block to convert the third signal to a second component of the ramping voltage signal.

20. The system of claim 19 , wherein:
the load block is coupled to the second circuits; and
the load block is configured to combine currents from the first and second circuits to generate the ramping voltage signal.

Assignees

• Cista Sys Corp

Inventors

• Lee Dennis Tunglin
• Zhang Guangbin

Classifications

• H03K4/02 Primary

  having stepped portions, e.g. staircase waveform · CPC title

• H03K4/08 Primary

  having sawtooth shape · CPC title

• H04N25/673

  by using reference sources · CPC title

• H04N25/677

  for reducing the column or line fixed pattern noise · CPC title

• H03K4/12

  in which a sawtooth voltage is produced across a capacitor · CPC title